Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

e6698305 · Linus Torvalds <[email protected]> · 2014-08-07 08:47:00 -07:00

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 3.17.  It contains:

   - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy  updates
   - MIPS ptrace updates and cleanups
   - various fixes that will also go to -stable
   - a number of cleanups and small non-critical fixes.
   - NUMA support for the Loongson 3.
   - more support for MSA
   - support for MAAR
   - various FP enhancements and fixes"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
  MIPS: jz4740: remove unnecessary null test before debugfs_remove
  MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive
  MIPS: ZBOOT: implement stack protector in compressed boot phase
  MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT
  MIPS: Bonito64: remove a duplicate define
  MIPS: Malta: initialise MAARs
  MIPS: Initialise MAARs
  MIPS: detect presence of MAARs
  MIPS: define MAAR register accessors & bits
  MIPS: mark MSA experimental
  MIPS: Don't build MSA support unless it can be used
  MIPS: consistently clear MSA flags when starting & copying threads
  MIPS: 16 byte align MSA vector context
  MIPS: disable preemption whilst initialising MSA
  MIPS: ensure MSA gets disabled during boot
  MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains
  MIPS: fix MSA context for tasks which don't use FP first
  MIPS: init upper 64b of vector registers when MSA is first used
  MIPS: save/disable MSA in lose_fpu
  MIPS: preserve scalar FP CSR when switching vector context
  ...

Commit: e669830526a0abaf301bf408df69cde33901ac63
Parents: ebb067d2 · 475d5928

Merge commit. Changes below are compared with the first parent: ebb067d2.

Changes

156 files changed · +5979 −3529

File	Status	Add	Del	Content
Documentation/kernel-parameters.txt	modified	+6	−0	View file
arch/mips/Kconfig	modified	+7	−2	View file
arch/mips/Makefile	modified	+3	−1	View file
arch/mips/alchemy/board-mtx1.c	modified	+2	−2	View file
arch/mips/alchemy/board-xxs1500.c	modified	+2	−2	View file
arch/mips/alchemy/common/Makefile	modified	+2	−2	View file
arch/mips/alchemy/common/clock.c	added	+1094	−0	View file
arch/mips/alchemy/common/clocks.c	deleted	+0	−105	View before deletion
arch/mips/alchemy/common/dbdma.c	modified	+11	−11	View file
arch/mips/alchemy/common/dma.c	modified	+8	−7	View file
arch/mips/alchemy/common/irq.c	modified	+2	−3	View file
arch/mips/alchemy/common/platform.c	modified	+13	−2	View file
arch/mips/alchemy/common/power.c	modified	+36	−38	View file
arch/mips/alchemy/common/setup.c	modified	+0	−15	View file
arch/mips/alchemy/common/time.c	modified	+10	−13	View file
arch/mips/alchemy/common/usb.c	modified	+40	−7	View file
arch/mips/alchemy/devboards/db1000.c	modified	+16	−3	View file
arch/mips/alchemy/devboards/db1200.c	modified	+28	−33	View file
arch/mips/alchemy/devboards/db1300.c	modified	+8	−1	View file
arch/mips/alchemy/devboards/db1550.c	modified	+20	−7	View file
arch/mips/alchemy/devboards/pm.c	modified	+15	−24	View file
arch/mips/bcm47xx/Kconfig	modified	+1	−4	View file
arch/mips/bcm47xx/bcm47xx_private.h	modified	+3	−0	View file
arch/mips/bcm47xx/board.c	modified	+22	−4	View file
arch/mips/bcm47xx/buttons.c	modified	+34	−4	View file
arch/mips/bcm47xx/leds.c	modified	+79	−13	View file
arch/mips/bcm47xx/prom.c	modified	+67	−1	View file
arch/mips/bcm47xx/setup.c	modified	+5	−2	View file
arch/mips/bcm47xx/sprom.c	modified	+48	−0	View file
arch/mips/bcm63xx/cpu.c	modified	+3	−8	View file
arch/mips/bcm63xx/dev-enet.c	modified	+0	−4	View file
arch/mips/bcm63xx/dev-spi.c	modified	+0	−4	View file
arch/mips/bcm63xx/gpio.c	modified	+0	−14	View file
arch/mips/bcm63xx/irq.c	modified	+269	−289	View file
arch/mips/bcm63xx/reset.c	modified	+0	−60	View file
arch/mips/boot/compressed/decompress.c	modified	+14	−0	View file
arch/mips/cavium-octeon/executive/cvmx-helper-board.c	modified	+22	−0	View file
arch/mips/cavium-octeon/oct_ilm.c	modified	+1	−2	View file
arch/mips/cavium-octeon/smp.c	modified	+12	−11	View file
arch/mips/configs/loongson3_defconfig	modified	+1	−1	View file
arch/mips/include/asm/Kbuild	modified	+1	−0	View file
arch/mips/include/asm/addrspace.h	modified	+1	−1	View file
arch/mips/include/asm/asmmacro.h	modified	+31	−0	View file
arch/mips/include/asm/bitops.h	modified	+7	−1	View file
arch/mips/include/asm/cop2.h	modified	+8	−0	View file
arch/mips/include/asm/cpu-features.h	modified	+9	−0	View file
arch/mips/include/asm/cpu-info.h	modified	+3	−2	View file
arch/mips/include/asm/cpu.h	modified	+33	−28	View file
arch/mips/include/asm/elf.h	modified	+0	−17	View file
arch/mips/include/asm/fpu.h	modified	+12	−7	View file
arch/mips/include/asm/gic.h	modified	+15	−26	View file
arch/mips/include/asm/maar.h	added	+109	−0	View file
arch/mips/include/asm/mach-au1x00/au1000.h	modified	+1082	−1433	View file
arch/mips/include/asm/mach-au1x00/au1000_dma.h	modified	+25	−25	View file
arch/mips/include/asm/mach-au1x00/gpio-au1000.h	modified	+26	−30	View file
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h	modified	+6	−1	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h	modified	+35	−163	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h	modified	+0	−46	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h	modified	+0	−31	View file
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h	modified	+8	−8	View file
arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	modified	+1	−1	View file
arch/mips/include/asm/mach-loongson/boot_param.h	modified	+4	−0	View file
arch/mips/include/asm/mach-loongson/kernel-entry-init.h	added	+52	−0	View file
arch/mips/include/asm/mach-loongson/loongson.h	modified	+9	−2	View file
arch/mips/include/asm/mach-loongson/machine.h	modified	+2	−2	View file
arch/mips/include/asm/mach-loongson/mmzone.h	added	+53	−0	View file
arch/mips/include/asm/mach-loongson/topology.h	added	+23	−0	View file
arch/mips/include/asm/mach-malta/irq.h	modified	+1	−0	View file
arch/mips/include/asm/mach-sead3/irq.h	modified	+1	−0	View file
arch/mips/include/asm/mips-boards/bonito64.h	modified	+0	−1	View file
arch/mips/include/asm/mipsregs.h	modified	+57	−1	View file
arch/mips/include/asm/mmu_context.h	modified	+10	−0	View file
arch/mips/include/asm/msa.h	modified	+18	−13	View file
arch/mips/include/asm/octeon/cvmx-bootinfo.h	modified	+2	−0	View file
arch/mips/include/asm/pgtable-32.h	modified	+12	−0	View file
arch/mips/include/asm/pgtable.h	modified	+27	−0	View file
arch/mips/include/asm/processor.h	modified	+8	−2	View file
arch/mips/include/asm/ptrace.h	modified	+5	−3	View file
arch/mips/include/asm/reg.h	modified	+1	−128	View file
arch/mips/include/asm/smp-cps.h	modified	+10	−2	View file
arch/mips/include/asm/smp.h	modified	+6	−0	View file
arch/mips/include/asm/sparsemem.h	modified	+1	−1	View file
arch/mips/include/asm/user.h	deleted	+0	−58	View before deletion
arch/mips/include/uapi/asm/ptrace.h	modified	+14	−11	View file
arch/mips/include/uapi/asm/reg.h	added	+206	−0	View file
arch/mips/jz4740/clock-debugfs.c	modified	+1	−2	View file
arch/mips/jz4740/platform.c	modified	+1	−1	View file
arch/mips/kernel/asm-offsets.c	modified	+1	−0	View file
arch/mips/kernel/binfmt_elfo32.c	modified	+0	−38	View file
arch/mips/kernel/cpu-probe.c	modified	+42	−3	View file
arch/mips/kernel/ftrace.c	modified	+47	−9	View file
arch/mips/kernel/irq-gic.c	modified	+30	−8	View file
arch/mips/kernel/mcount.S	modified	+13	−0	View file
arch/mips/kernel/perf_event_mipsxx.c	modified	+34	−8	View file
arch/mips/kernel/pm-cps.c	modified	+9	−1	View file
arch/mips/kernel/proc.c	modified	+2	−0	View file
arch/mips/kernel/process.c	modified	+4	−56	View file
arch/mips/kernel/ptrace.c	modified	+177	−46	View file
arch/mips/kernel/ptrace32.c	modified	+6	−4	View file
arch/mips/kernel/r4k_switch.S	modified	+8	−1	View file
arch/mips/kernel/rtlx-cmp.c	modified	+3	−0	View file
arch/mips/kernel/rtlx-mt.c	modified	+3	−0	View file
arch/mips/kernel/scall32-o32.S	modified	+2	−4	View file
arch/mips/kernel/scall64-64.S	modified	+2	−2	View file
arch/mips/kernel/scall64-n32.S	modified	+6	−6	View file
arch/mips/kernel/scall64-o32.S	modified	+4	−4	View file
arch/mips/kernel/setup.c	modified	+21	−1	View file
arch/mips/kernel/smp-cps.c	modified	+8	−4	View file
arch/mips/kernel/smp-mt.c	modified	+2	−0	View file
arch/mips/kernel/smp.c	modified	+25	−1	View file
arch/mips/kernel/traps.c	modified	+52	−9	View file
arch/mips/kernel/unaligned.c	modified	+0	−1	View file
arch/mips/loongson/Kconfig	modified	+5	−4	View file
arch/mips/loongson/Platform	modified	+1	−1	View file
arch/mips/loongson/common/env.c	modified	+48	−1	View file
arch/mips/loongson/common/init.c	modified	+4	−0	View file
arch/mips/loongson/common/pm.c	modified	+4	−4	View file
arch/mips/loongson/lemote-2f/clock.c	modified	+2	−2	View file
arch/mips/loongson/lemote-2f/reset.c	modified	+1	−1	View file
arch/mips/loongson/loongson-3/Makefile	modified	+3	−1	View file
arch/mips/loongson/loongson-3/cop2-ex.c	added	+63	−0	View file
arch/mips/loongson/loongson-3/irq.c	modified	+20	−6	View file
arch/mips/loongson/loongson-3/numa.c	added	+291	−0	View file
arch/mips/loongson/loongson-3/smp.c	modified	+292	−95	View file
arch/mips/loongson/loongson-3/smp.h	modified	+19	−18	View file
arch/mips/math-emu/cp1emu.c	modified	+1	−1	View file
arch/mips/mm/c-r4k.c	modified	+4	−4	View file
arch/mips/mm/init.c	modified	+33	−0	View file
arch/mips/mm/tlb-r3k.c	modified	+1	−1	View file
arch/mips/mm/tlb-r4k.c	modified	+59	−0	View file
arch/mips/mm/tlbex.c	modified	+96	−2	View file
arch/mips/mti-malta/malta-int.c	modified	+19	−8	View file
arch/mips/mti-malta/malta-memory.c	modified	+26	−0	View file
arch/mips/pci/Makefile	modified	+1	−1	View file
arch/mips/pci/ops-tx4927.c	modified	+0	−2	View file
arch/mips/pci/pci-alchemy.c	modified	+23	−1	View file
arch/mips/ralink/of.c	modified	+1	−1	View file
arch/mips/rb532/devices.c	modified	+5	−23	View file
arch/mips/sgi-ip22/ip22-gio.c	modified	+9	−1	View file
arch/mips/txx9/generic/7segled.c	modified	+11	−3	View file
arch/mips/txx9/generic/pci.c	modified	+2	−2	View file
arch/mips/txx9/generic/setup.c	modified	+19	−10	View file
drivers/cpufreq/loongson2_cpufreq.c	modified	+3	−3	View file
drivers/mmc/host/au1xmmc.c	modified	+107	−91	View file
drivers/mtd/nand/au1550nd.c	modified	+13	−16	View file
drivers/net/ethernet/amd/au1000_eth.c	modified	+137	−12	View file
drivers/net/irda/au1k_ir.c	modified	+46	−2	View file
drivers/rtc/rtc-au1xxx.c	modified	+8	−10	View file
drivers/spi/spi-au1550.c	modified	+33	−33	View file
drivers/video/fbdev/au1100fb.c	modified	+24	−15	View file
drivers/video/fbdev/au1100fb.h	modified	+1	−0	View file
drivers/video/fbdev/au1200fb.c	modified	+38	−43	View file
drivers/watchdog/octeon-wdt-main.c	modified	+34	−28	View file
sound/soc/au1x/psc-ac97.c	modified	+70	−70	View file
sound/soc/au1x/psc-i2s.c	modified	+50	−50	View file
sound/soc/au1x/psc.h	modified	+11	−11	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/kernel-parameters.txt

View file

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 21ae0e4..664fd88 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -571,6 +571,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			trust validation.
 			format: { id:<keyid> | builtin }
 
+	cca=		[MIPS] Override the kernel pages' cache coherency
+			algorithm.  Accepted values range from 0 to 7
+			inclusive. See arch/mips/include/asm/pgtable-bits.h
+			for platform specific values (SB1, Loongson3 and
+			others).
+
 	ccw_timeout_log [S390]
 			See Documentation/s390/CommonIO for details.
 

arch/mips/Kconfig

View file

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 10f270b..900c7e5 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -71,6 +71,7 @@ config MIPS_ALCHEMY
 	select SYS_SUPPORTS_APM_EMULATION
 	select ARCH_REQUIRE_GPIOLIB
 	select SYS_SUPPORTS_ZBOOT
+	select COMMON_CLK
 
 config AR7
 	bool "Texas Instruments AR7"
@@ -129,6 +130,8 @@ config BCM47XX
 	select SYS_SUPPORTS_MIPS16
 	select SYS_HAS_EARLY_PRINTK
 	select USE_GENERIC_EARLY_PRINTK_8250
+	select GPIOLIB
+	select LEDS_GPIO_REGISTER
 	help
 	 Support for BCM47XX based boards
 
@@ -137,6 +140,7 @@ config BCM63XX
 	select BOOT_RAW
 	select CEVT_R4K
 	select CSRC_R4K
+	select SYNC_R4K
 	select DMA_NONCOHERENT
 	select IRQ_CPU
 	select SYS_SUPPORTS_32BIT_KERNEL
@@ -2056,6 +2060,7 @@ config MIPS_CPS
 	  support is unavailable.
 
 config MIPS_CPS_PM
+	select MIPS_CPC
 	bool
 
 config MIPS_GIC_IPI
@@ -2109,9 +2114,9 @@ config CPU_MICROMIPS
 	  microMIPS ISA
 
 config CPU_HAS_MSA
-	bool "Support for the MIPS SIMD Architecture"
+	bool "Support for the MIPS SIMD Architecture (EXPERIMENTAL)"
 	depends on CPU_SUPPORTS_MSA
-	default y
+	depends on 64BIT || MIPS_O32_FP64_SUPPORT
 	help
 	  MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
 	  and a set of SIMD instructions to operate on them. When this option

arch/mips/Makefile

View file

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index a8521de..9336509 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -151,8 +151,10 @@ cflags-$(CONFIG_CPU_NEVADA)	+= $(call cc-option,-march=rm5200,-march=r5000) \
 			-Wa,--trap
 cflags-$(CONFIG_CPU_RM7000)	+= $(call cc-option,-march=rm7000,-march=r5000) \
 			-Wa,--trap
-cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1 -mno-mdmx -mno-mips3d,-march=r5000) \
+cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1,-march=r5000) \
 			-Wa,--trap
+cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mdmx)
+cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mips3d)
 cflags-$(CONFIG_CPU_R8000)	+= -march=r8000 -Wa,--trap
 cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=r8000) \
 			-Wa,--trap

arch/mips/alchemy/board-mtx1.c

View file

diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 25a59a2..1e3b102 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -85,10 +85,10 @@ void __init board_setup(void)
 #endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
 
 	/* Initialize sys_pinfunc */
-	au_writel(SYS_PF_NI2, SYS_PINFUNC);
+	alchemy_wrsys(SYS_PF_NI2, AU1000_SYS_PINFUNC);
 
 	/* Initialize GPIO */
-	au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
+	alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR);
 	alchemy_gpio_direction_output(0, 0);	/* Disable M66EN (PCI 66MHz) */
 	alchemy_gpio_direction_output(3, 1);	/* Disable PCI CLKRUN# */
 	alchemy_gpio_direction_output(1, 1);	/* Enable EXT_IO3 */

arch/mips/alchemy/board-xxs1500.c

View file

diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c
index 3fb814b..0fc53e0 100644
--- a/arch/mips/alchemy/board-xxs1500.c
+++ b/arch/mips/alchemy/board-xxs1500.c
@@ -87,9 +87,9 @@ void __init board_setup(void)
 	alchemy_gpio2_enable();
 
 	/* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
-	pin_func  = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
+	pin_func  = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PF_UR3;
 	pin_func |= SYS_PF_UR3;
-	au_writel(pin_func, SYS_PINFUNC);
+	alchemy_wrsys(pin_func, AU1000_SYS_PINFUNC);
 
 	/* Enable UART */
 	alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);

arch/mips/alchemy/common/Makefile

View file

diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index cb83d8d..f64744f 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -5,8 +5,8 @@
 # Makefile for the Alchemy Au1xx0 CPUs, generic files.
 #
 
-obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
-	sleeper.o dma.o dbdma.o vss.o irq.o usb.o
+obj-y += prom.o time.o clock.o platform.o power.o \
+	 setup.o sleeper.o dma.o dbdma.o vss.o irq.o usb.o
 
 # optional gpiolib support
 ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)

arch/mips/alchemy/common/clock.c

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diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
new file mode 100644
index 0000000..d7557cd
--- /dev/null
+++ b/arch/mips/alchemy/common/clock.c
@@ -0,0 +1,1094 @@
+/*
+ * Alchemy clocks.
+ *
+ * Exposes all configurable internal clock sources to the clk framework.
+ *
+ * We have:
+ *  - Root source, usually 12MHz supplied by an external crystal
+ *  - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
+ *
+ * Dividers:
+ *  - 6 clock dividers with:
+ *   * selectable source [one of the PLLs],
+ *   * output divided between [2 .. 512 in steps of 2] (!Au1300)
+ *     or [1 .. 256 in steps of 1] (Au1300),
+ *   * can be enabled individually.
+ *
+ * - up to 6 "internal" (fixed) consumers which:
+ *   * take either AUXPLL or one of the above 6 dividers as input,
+ *   * divide this input by 1, 2, or 4 (and 3 on Au1300).
+ *   * can be disabled separately.
+ *
+ * Misc clocks:
+ * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
+ *    depends on board design and should be set by bootloader, read-only.
+ * - peripheral clock: half the rate of sysbus clock, source for a lot
+ *    of peripheral blocks, read-only.
+ * - memory clock: clk rate to main memory chips, depends on board
+ *    design and is read-only,
+ * - lrclk: the static bus clock signal for synchronous operation.
+ *    depends on board design, must be set by bootloader,
+ *    but may be required to correctly configure devices attached to
+ *    the static bus. The Au1000/1500/1100 manuals call it LCLK, on
+ *    later models it's called RCLK.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk-private.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <asm/mach-au1x00/au1000.h>
+
+/* Base clock: 12MHz is the default in all databooks, and I haven't
+ * found any board yet which uses a different rate.
+ */
+#define ALCHEMY_ROOTCLK_RATE	12000000
+
+/*
+ * the internal sources which can be driven by the PLLs and dividers.
+ * Names taken from the databooks, refer to them for more information,
+ * especially which ones are share a clock line.
+ */
+static const char * const alchemy_au1300_intclknames[] = {
+	"lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
+	"EXTCLK0", "EXTCLK1"
+};
+
+static const char * const alchemy_au1200_intclknames[] = {
+	"lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1"
+};
+
+static const char * const alchemy_au1550_intclknames[] = {
+	"usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
+	"EXTCLK0", "EXTCLK1"
+};
+
+static const char * const alchemy_au1100_intclknames[] = {
+	"usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1"
+};
+
+static const char * const alchemy_au1500_intclknames[] = {
+	NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
+};
+
+static const char * const alchemy_au1000_intclknames[] = {
+	"irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
+	"EXTCLK1"
+};
+
+/* aliases for a few on-chip sources which are either shared
+ * or have gone through name changes.
+ */
+static struct clk_aliastable {
+	char *alias;
+	char *base;
+	int cputype;
+} alchemy_clk_aliases[] __initdata = {
+	{ "usbh_clk", "usb_clk",    ALCHEMY_CPU_AU1100 },
+	{ "usbd_clk", "usb_clk",    ALCHEMY_CPU_AU1100 },
+	{ "irda_clk", "usb_clk",    ALCHEMY_CPU_AU1100 },
+	{ "usbh_clk", "usb_clk",    ALCHEMY_CPU_AU1550 },
+	{ "usbd_clk", "usb_clk",    ALCHEMY_CPU_AU1550 },
+	{ "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 },
+	{ "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 },
+	{ "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 },
+	{ "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 },
+	{ "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
+	{ "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
+	{ "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
+	{ "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
+
+	{ NULL, NULL, 0 },
+};
+
+#define IOMEM(x)	((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
+
+/* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
+static spinlock_t alchemy_clk_fg0_lock;
+static spinlock_t alchemy_clk_fg1_lock;
+static spinlock_t alchemy_clk_csrc_lock;
+
+/* CPU Core clock *****************************************************/
+
+static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
+					    unsigned long parent_rate)
+{
+	unsigned long t;
+
+	/*
+	 * On early Au1000, sys_cpupll was write-only. Since these
+	 * silicon versions of Au1000 are not sold, we don't bend
+	 * over backwards trying to determine the frequency.
+	 */
+	if (unlikely(au1xxx_cpu_has_pll_wo()))
+		t = 396000000;
+	else {
+		t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
+		t *= parent_rate;
+	}
+
+	return t;
+}
+
+static struct clk_ops alchemy_clkops_cpu = {
+	.recalc_rate	= alchemy_clk_cpu_recalc,
+};
+
+static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
+						int ctype)
+{
+	struct clk_init_data id;
+	struct clk_hw *h;
+
+	h = kzalloc(sizeof(*h), GFP_KERNEL);
+	if (!h)
+		return ERR_PTR(-ENOMEM);
+
+	id.name = ALCHEMY_CPU_CLK;
+	id.parent_names = &parent_name;
+	id.num_parents = 1;
+	id.flags = CLK_IS_BASIC;
+	id.ops = &alchemy_clkops_cpu;
+	h->init = &id;
+
+	return clk_register(NULL, h);
+}
+
+/* AUXPLLs ************************************************************/
+
+struct alchemy_auxpll_clk {
+	struct clk_hw hw;
+	unsigned long reg;	/* au1300 has also AUXPLL2 */
+	int maxmult;		/* max multiplier */
+};
+#define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
+
+static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw,
+					    unsigned long parent_rate)
+{
+	struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
+
+	return (alchemy_rdsys(a->reg) & 0xff) * parent_rate;
+}
+
+static int alchemy_clk_aux_setr(struct clk_hw *hw,
+				unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
+	unsigned long d = rate;
+
+	if (rate)
+		d /= parent_rate;
+	else
+		d = 0;
+
+	/* minimum is 84MHz, max is 756-1032 depending on variant */
+	if (((d < 7) && (d != 0)) || (d > a->maxmult))
+		return -EINVAL;
+
+	alchemy_wrsys(d, a->reg);
+	return 0;
+}
+
+static long alchemy_clk_aux_roundr(struct clk_hw *hw,
+					    unsigned long rate,
+					    unsigned long *parent_rate)
+{
+	struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
+	unsigned long mult;
+
+	if (!rate || !*parent_rate)
+		return 0;
+
+	mult = rate / (*parent_rate);
+
+	if (mult && (mult < 7))
+		mult = 7;
+	if (mult > a->maxmult)
+		mult = a->maxmult;
+
+	return (*parent_rate) * mult;
+}
+
+static struct clk_ops alchemy_clkops_aux = {
+	.recalc_rate	= alchemy_clk_aux_recalc,
+	.set_rate	= alchemy_clk_aux_setr,
+	.round_rate	= alchemy_clk_aux_roundr,
+};
+
+static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
+						char *name, int maxmult,
+						unsigned long reg)
+{
+	struct clk_init_data id;
+	struct clk *c;
+	struct alchemy_auxpll_clk *a;
+
+	a = kzalloc(sizeof(*a), GFP_KERNEL);
+	if (!a)
+		return ERR_PTR(-ENOMEM);
+
+	id.name = name;
+	id.parent_names = &parent_name;
+	id.num_parents = 1;
+	id.flags = CLK_GET_RATE_NOCACHE;
+	id.ops = &alchemy_clkops_aux;
+
+	a->reg = reg;
+	a->maxmult = maxmult;
+	a->hw.init = &id;
+
+	c = clk_register(NULL, &a->hw);
+	if (!IS_ERR(c))
+		clk_register_clkdev(c, name, NULL);
+	else
+		kfree(a);
+
+	return c;
+}
+
+/* sysbus_clk *********************************************************/
+
+static struct clk __init  *alchemy_clk_setup_sysbus(const char *pn)
+{
+	unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
+	struct clk *c;
+
+	c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
+				      pn, 0, 1, v);
+	if (!IS_ERR(c))
+		clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);
+	return c;
+}
+
+/* Peripheral Clock ***************************************************/
+
+static struct clk __init *alchemy_clk_setup_periph(const char *pn)
+{
+	/* Peripheral clock runs at half the rate of sysbus clk */
+	struct clk *c;
+
+	c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
+				      pn, 0, 1, 2);
+	if (!IS_ERR(c))
+		clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);
+	return c;
+}
+
+/* mem clock **********************************************************/
+
+static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
+{
+	void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR);
+	unsigned long v;
+	struct clk *c;
+	int div;
+
+	switch (ct) {
+	case ALCHEMY_CPU_AU1550:
+	case ALCHEMY_CPU_AU1200:
+		v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
+		div = (v & (1 << 15)) ? 1 : 2;
+		break;
+	case ALCHEMY_CPU_AU1300:
+		v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
+		div = (v & (1 << 31)) ? 1 : 2;
+		break;
+	case ALCHEMY_CPU_AU1000:
+	case ALCHEMY_CPU_AU1500:
+	case ALCHEMY_CPU_AU1100:
+	default:
+		div = 2;
+		break;
+	}
+
+	c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
+				      0, 1, div);
+	if (!IS_ERR(c))
+		clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);
+	return c;
+}
+
+/* lrclk: external synchronous static bus clock ***********************/
+
+static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
+{
+	/* MEM_STCFG0[15:13] = divisor.
+	 * L/RCLK = periph_clk / (divisor + 1)
+	 * On Au1000, Au1500, Au1100 it's called LCLK,
+	 * on later models it's called RCLK, but it's the same thing.
+	 */
+	struct clk *c;
+	unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
+
+	v = (v & 7) + 1;
+	c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
+				      pn, 0, 1, v);
+	if (!IS_ERR(c))
+		clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);
+	return c;
+}
+
+/* Clock dividers and muxes *******************************************/
+
+/* data for fgen and csrc mux-dividers */
+struct alchemy_fgcs_clk {
+	struct clk_hw hw;
+	spinlock_t *reglock;	/* register lock		  */
+	unsigned long reg;	/* SYS_FREQCTRL0/1		  */
+	int shift;		/* offset in register		  */
+	int parent;		/* parent before disable [Au1300] */
+	int isen;		/* is it enabled?		  */
+	int *dt;		/* dividertable for csrc	  */
+};
+#define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
+
+static long alchemy_calc_div(unsigned long rate, unsigned long prate,
+			       int scale, int maxdiv, unsigned long *rv)
+{
+	long div1, div2;
+
+	div1 = prate / rate;
+	if ((prate / div1) > rate)
+		div1++;
+
+	if (scale == 2) {	/* only div-by-multiple-of-2 possible */
+		if (div1 & 1)
+			div1++;	/* stay <=prate */
+	}
+
+	div2 = (div1 / scale) - 1;	/* value to write to register */
+
+	if (div2 > maxdiv)
+		div2 = maxdiv;
+	if (rv)
+		*rv = div2;
+
+	div1 = ((div2 + 1) * scale);
+	return div1;
+}
+
+static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
+					unsigned long *best_parent_rate,
+					struct clk **best_parent_clk,
+					int scale, int maxdiv)
+{
+	struct clk *pc, *bpc, *free;
+	long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;
+	int j;
+
+	lastdiff = INT_MAX;
+	bpr = 0;
+	bpc = NULL;
+	br = -EINVAL;
+	free = NULL;
+
+	/* look at the rates each enabled parent supplies and select
+	 * the one that gets closest to but not over the requested rate.
+	 */
+	for (j = 0; j < 7; j++) {
+		pc = clk_get_parent_by_index(hw->clk, j);
+		if (!pc)
+			break;
+
+		/* if this parent is currently unused, remember it.
+		 * XXX: I know it's a layering violation, but it works
+		 * so well.. (if (!clk_has_active_children(pc)) )
+		 */
+		if (pc->prepare_count == 0) {
+			if (!free)
+				free = pc;
+		}
+
+		pr = clk_get_rate(pc);
+		if (pr < rate)
+			continue;
+
+		/* what can hardware actually provide */
+		tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
+		nr = pr / tdv;
+		diff = rate - nr;
+		if (nr > rate)
+			continue;
+
+		if (diff < lastdiff) {
+			lastdiff = diff;
+			bpr = pr;
+			bpc = pc;
+			br = nr;
+		}
+		if (diff == 0)
+			break;
+	}
+
+	/* if we couldn't get the exact rate we wanted from the enabled
+	 * parents, maybe we can tell an available disabled/inactive one
+	 * to give us a rate we can divide down to the requested rate.
+	 */
+	if (lastdiff && free) {
+		for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {
+			tpr = rate * j;
+			if (tpr < 0)
+				break;
+			pr = clk_round_rate(free, tpr);
+
+			tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
+			nr = pr / tdv;
+			diff = rate - nr;
+			if (nr > rate)
+				continue;
+			if (diff < lastdiff) {
+				lastdiff = diff;
+				bpr = pr;
+				bpc = free;
+				br = nr;
+			}
+			if (diff == 0)
+				break;
+		}
+	}
+
+	*best_parent_rate = bpr;
+	*best_parent_clk = bpc;
+	return br;
+}
+
+static int alchemy_clk_fgv1_en(struct clk_hw *hw)
+{
+	struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
+	unsigned long v, flags;