Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

ef1a8de8 · Linus Torvalds <[email protected]> · 2010-02-27 13:26:18 -08:00

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (88 commits)
  powerpc: Fix lwsync feature fixup vs. modules on 64-bit
  powerpc: Convert pmc_owner_lock to raw_spinlock
  powerpc: Convert die.lock to raw_spinlock
  powerpc: Convert tlbivax_lock to raw_spinlock
  powerpc: Convert mpic locks to raw_spinlock
  powerpc: Convert pmac_pic_lock to raw_spinlock
  powerpc: Convert big_irq_lock to raw_spinlock
  powerpc: Convert feature_lock to raw_spinlock
  powerpc: Convert i8259_lock to raw_spinlock
  powerpc: Convert beat_htab_lock to raw_spinlock
  powerpc: Convert confirm_error_lock to raw_spinlock
  powerpc: Convert ipic_lock to raw_spinlock
  powerpc: Convert native_tlbie_lock to raw_spinlock
  powerpc: Convert beatic_irq_mask_lock to raw_spinlock
  powerpc: Convert nv_lock to raw_spinlock
  powerpc: Convert context_lock to raw_spinlock
  powerpc/85xx: Add NOR, LEDs and PIB support for MPC8568E-MDS boards
  powerpc/86xx: Enable VME driver on the GE SBC610
  powerpc/86xx: Enable VME driver on the GE PPC9A
  powerpc/86xx: Add MSI section to GE PPC9A DTS
  ...

Commit: ef1a8de8ea004a689b2aa9f5cefcba2b1a0262f2
Parents: 1c32fd0c · 3d98ffbf

Merge commit. Changes below are compared with the first parent: 1c32fd0c.

Changes

128 files changed · +4900 −803

File	Status	Add	Del	Content
Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt	added	+70	−0	View file
Documentation/powerpc/dts-bindings/fsl/spi.txt	modified	+7	−0	View file
Documentation/powerpc/ptrace.txt	added	+134	−0	View file
arch/powerpc/Kconfig	modified	+28	−1	View file
arch/powerpc/boot/dts/arches.dts	modified	+12	−0	View file
arch/powerpc/boot/dts/gef_ppc9a.dts	modified	+16	−0	View file
arch/powerpc/boot/dts/gef_sbc310.dts	modified	+18	−1	View file
arch/powerpc/boot/dts/gef_sbc610.dts	modified	+58	−8	View file
arch/powerpc/boot/dts/glacier.dts	modified	+67	−9	View file
arch/powerpc/boot/dts/katmai.dts	modified	+52	−19	View file
arch/powerpc/boot/dts/mpc5121ads.dts	modified	+33	−22	View file
arch/powerpc/boot/dts/mpc8568mds.dts	modified	+62	−3	View file
arch/powerpc/configs/44x/katmai_defconfig	modified	+89	−5	View file
arch/powerpc/configs/86xx/gef_ppc9a_defconfig	modified	+46	−1	View file
arch/powerpc/configs/86xx/gef_sbc610_defconfig	modified	+54	−11	View file
arch/powerpc/configs/mpc512x_defconfig	added	+1694	−0	View file
arch/powerpc/configs/ppc64_defconfig	modified	+44	−31	View file
arch/powerpc/configs/pseries_defconfig	modified	+35	−28	View file
arch/powerpc/include/asm/asm-compat.h	modified	+3	−2	View file
arch/powerpc/include/asm/atomic.h	modified	+24	−24	View file
arch/powerpc/include/asm/bitops.h	modified	+30	−26	View file
arch/powerpc/include/asm/cputable.h	modified	+2	−2	View file
arch/powerpc/include/asm/cputime.h	modified	+3	−4	View file
arch/powerpc/include/asm/feature-fixups.h	modified	+1	−1	View file
arch/powerpc/include/asm/futex.h	modified	+3	−3	View file
arch/powerpc/include/asm/hardirq.h	modified	+29	−1	View file
arch/powerpc/include/asm/local.h	modified	+6	−6	View file
arch/powerpc/include/asm/mpc5121.h	added	+24	−0	View file
arch/powerpc/include/asm/mpc52xx_psc.h	modified	+4	−0	View file
arch/powerpc/include/asm/mpic.h	modified	+1	−1	View file
arch/powerpc/include/asm/mutex.h	modified	+3	−3	View file
arch/powerpc/include/asm/param.h	modified	+1	−22	View file
arch/powerpc/include/asm/pmac_feature.h	modified	+1	−1	View file
arch/powerpc/include/asm/ppc-opcode.h	modified	+18	−0	View file
arch/powerpc/include/asm/ppc-pci.h	modified	+5	−0	View file
arch/powerpc/include/asm/processor.h	modified	+34	−2	View file
arch/powerpc/include/asm/ptrace.h	modified	+77	−0	View file
arch/powerpc/include/asm/reg_booke.h	modified	+95	−1	View file
arch/powerpc/include/asm/spinlock.h	modified	+17	−15	View file
arch/powerpc/include/asm/synch.h	modified	+8	−4	View file
arch/powerpc/include/asm/system.h	modified	+13	−8	View file
arch/powerpc/include/asm/topology.h	modified	+27	−21	View file
arch/powerpc/kernel/entry_64.S	modified	+1	−2	View file
arch/powerpc/kernel/firmware.c	modified	+1	−1	View file
arch/powerpc/kernel/head_fsl_booke.S	modified	+2	−2	View file
arch/powerpc/kernel/irq.c	modified	+93	−47	View file
arch/powerpc/kernel/kgdb.c	modified	+1	−1	View file
arch/powerpc/kernel/kprobes.c	modified	+2	−2	View file
arch/powerpc/kernel/lparcfg.c	modified	+5	−5	View file
arch/powerpc/kernel/nvram_64.c	modified	+3	−3	View file
arch/powerpc/kernel/pci_of_scan.c	modified	+1	−1	View file
arch/powerpc/kernel/pmc.c	modified	+5	−5	View file
arch/powerpc/kernel/process.c	modified	+96	−20	View file
arch/powerpc/kernel/prom_init.c	modified	+79	−2	View file
arch/powerpc/kernel/ptrace.c	modified	+488	−28	View file
arch/powerpc/kernel/signal.c	modified	+2	−4	View file
arch/powerpc/kernel/signal_32.c	modified	+10	−6	View file
arch/powerpc/kernel/time.c	modified	+6	−4	View file
arch/powerpc/kernel/traps.c	modified	+95	−33	View file
arch/powerpc/lib/copypage_64.S	modified	+14	−14	View file
arch/powerpc/lib/copyuser_64.S	modified	+57	−23	View file
arch/powerpc/lib/feature-fixups.c	modified	+2	−1	View file
arch/powerpc/mm/40x_mmu.c	modified	+2	−2	View file
arch/powerpc/mm/hash_native_64.c	modified	+9	−10	View file
arch/powerpc/mm/mmu_context_hash64.c	modified	+5	−5	View file
arch/powerpc/mm/mmu_context_nohash.c	modified	+7	−7	View file
arch/powerpc/mm/tlb_low_64e.S	modified	+1	−1	View file
arch/powerpc/mm/tlb_nohash.c	modified	+3	−3	View file
arch/powerpc/platforms/512x/clock.c	modified	+1	−5	View file
arch/powerpc/platforms/512x/mpc5121_ads.c	modified	+2	−1	View file
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c	modified	+1	−1	View file
arch/powerpc/platforms/512x/mpc5121_generic.c	modified	+2	−1	View file
arch/powerpc/platforms/512x/mpc512x.h	modified	+3	−0	View file
arch/powerpc/platforms/512x/mpc512x_shared.c	modified	+43	−0	View file
arch/powerpc/platforms/85xx/mpc85xx_mds.c	modified	+3	−0	View file
arch/powerpc/platforms/85xx/socrates_fpga_pic.c	modified	+1	−1	View file
arch/powerpc/platforms/85xx/stx_gp3.c	modified	+1	−1	View file
arch/powerpc/platforms/cell/beat_htab.c	modified	+12	−12	View file
arch/powerpc/platforms/cell/beat_interrupt.c	modified	+10	−10	View file
arch/powerpc/platforms/cell/interrupt.c	modified	+2	−2	View file
arch/powerpc/platforms/cell/spider-pic.c	modified	+1	−1	View file
arch/powerpc/platforms/iseries/irq.c	modified	+1	−1	View file
arch/powerpc/platforms/iseries/proc.c	modified	+1	−1	View file
arch/powerpc/platforms/iseries/setup.c	modified	+1	−1	View file
arch/powerpc/platforms/powermac/bootx_init.c	modified	+2	−2	View file
arch/powerpc/platforms/powermac/feature.c	modified	+3	−3	View file
arch/powerpc/platforms/powermac/nvram.c	modified	+7	−7	View file
arch/powerpc/platforms/powermac/pfunc_base.c	modified	+12	−12	View file
arch/powerpc/platforms/powermac/pic.c	modified	+20	−20	View file
arch/powerpc/platforms/pseries/eeh.c	modified	+9	−9	View file
arch/powerpc/platforms/pseries/eeh_driver.c	modified	+5	−5	View file
arch/powerpc/platforms/pseries/eeh_event.c	modified	+1	−1	View file
arch/powerpc/platforms/pseries/hotplug-cpu.c	modified	+5	−17	View file
arch/powerpc/platforms/pseries/hvCall_inst.c	modified	+2	−2	View file
arch/powerpc/platforms/pseries/pci_dlpar.c	modified	+1	−1	View file
arch/powerpc/platforms/pseries/phyp_dump.c	modified	+3	−3	View file
arch/powerpc/platforms/pseries/smp.c	modified	+2	−2	View file
arch/powerpc/platforms/pseries/xics.c	modified	+14	−18	View file
arch/powerpc/sysdev/cpm1.c	modified	+1	−1	View file
arch/powerpc/sysdev/cpm2_pic.c	modified	+1	−1	View file
arch/powerpc/sysdev/fsl_msi.c	modified	+1	−1	View file
arch/powerpc/sysdev/i8259.c	modified	+12	−12	View file
arch/powerpc/sysdev/ipic.c	modified	+11	−11	View file
arch/powerpc/sysdev/mpc8xx_pic.c	modified	+1	−1	View file
arch/powerpc/sysdev/mpic.c	modified	+20	−20	View file
arch/powerpc/sysdev/mpic_pasemi_msi.c	modified	+1	−1	View file
arch/powerpc/sysdev/mv64x60_dev.c	modified	+3	−0	View file
arch/powerpc/sysdev/ppc4xx_soc.c	modified	+2	−1	View file
arch/powerpc/sysdev/qe_lib/qe_ic.c	modified	+2	−2	View file
arch/powerpc/sysdev/qe_lib/qe_io.c	modified	+4	−4	View file
arch/powerpc/sysdev/uic.c	modified	+1	−1	View file
arch/powerpc/xmon/xmon.c	modified	+1	−1	View file
drivers/block/viodasd.c	modified	+36	−50	View file
drivers/char/hvc_console.c	modified	+3	−3	View file
drivers/char/hvc_console.h	modified	+2	−2	View file
drivers/hwmon/ams/ams-core.c	modified	+7	−4	View file
drivers/hwmon/ams/ams-i2c.c	modified	+2	−0	View file
drivers/hwmon/ams/ams-pmu.c	modified	+2	−0	View file
drivers/hwmon/ams/ams.h	modified	+1	−0	View file
drivers/macintosh/therm_adt746x.c	modified	+25	−11	View file
drivers/ps3/ps3av.c	modified	+1	−1	View file
drivers/rtc/Kconfig	modified	+10	−0	View file
drivers/rtc/Makefile	modified	+1	−0	View file
drivers/rtc/rtc-mpc5121.c	added	+387	−0	View file
drivers/serial/mpc52xx_uart.c	modified	+236	−15	View file
drivers/video/fsl-diu-fb.c	modified	+5	−0	View file
include/linux/lmb.h	modified	+1	−0	View file
lib/lmb.c	modified	+11	−2	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt

View file

diff --git a/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
new file mode 100644
index 0000000..8832e87
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
@@ -0,0 +1,70 @@
+MPC5121 PSC Device Tree Bindings
+
+PSC in UART mode
+----------------
+
+For PSC in UART mode the needed PSC serial devices
+are specified by fsl,mpc5121-psc-uart nodes in the
+fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
+Controller node fsl,mpc5121-psc-fifo is requered there:
+
+fsl,mpc5121-psc-uart nodes
+--------------------------
+
+Required properties :
+ - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
+ - cell-index : Index of the PSC in hardware
+ - reg : Offset and length of the register set for the PSC device
+ - interrupts : <a b> where a is the interrupt number of the
+   PSC FIFO Controller and b is a field that represents an
+   encoding of the sense and level information for the interrupt.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+
+Recommended properties :
+ - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
+ - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
+
+
+fsl,mpc5121-psc-fifo node
+-------------------------
+
+Required properties :
+ - compatible : Should be "fsl,mpc5121-psc-fifo"
+ - reg : Offset and length of the register set for the PSC
+         FIFO Controller
+ - interrupts : <a b> where a is the interrupt number of the
+   PSC FIFO Controller and b is a field that represents an
+   encoding of the sense and level information for the interrupt.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+
+
+Example for a board using PSC0 and PSC1 devices in serial mode:
+
+serial@11000 {
+	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+	cell-index = <0>;
+	reg = <0x11000 0x100>;
+	interrupts = <40 0x8>;
+	interrupt-parent = < &ipic >;
+	fsl,rx-fifo-size = <16>;
+	fsl,tx-fifo-size = <16>;
+};
+
+serial@11100 {
+	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+	cell-index = <1>;
+	reg = <0x11100 0x100>;
+	interrupts = <40 0x8>;
+	interrupt-parent = < &ipic >;
+	fsl,rx-fifo-size = <16>;
+	fsl,tx-fifo-size = <16>;
+};
+
+pscfifo@11f00 {
+	compatible = "fsl,mpc5121-psc-fifo";
+	reg = <0x11f00 0x100>;
+	interrupts = <40 0x8>;
+	interrupt-parent = < &ipic >;
+};

Documentation/powerpc/dts-bindings/fsl/spi.txt

View file

diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index e7d9a34..80510c0 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -13,6 +13,11 @@ Required properties:
 - interrupt-parent : the phandle for the interrupt controller that
   services interrupts for this device.
 
+Optional properties:
+- gpios : specifies the gpio pins to be used for chipselects.
+  The gpios will be referred to as reg = <index> in the SPI child nodes.
+  If unspecified, a single SPI device without a chip select can be used.
+
 Example:
 	spi@4c0 {
 		cell-index = <0>;
@@ -21,4 +26,6 @@ Example:
 		interrupts = <82 0>;
 		interrupt-parent = <700>;
 		mode = "cpu";
+		gpios = <&gpio 18 1	// device reg=<0>
+			 &gpio 19 1>;	// device reg=<1>
 	};

Documentation/powerpc/ptrace.txt

View file

diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.txt
new file mode 100644
index 0000000..f4a5499
--- /dev/null
+++ b/Documentation/powerpc/ptrace.txt
@@ -0,0 +1,134 @@
+GDB intends to support the following hardware debug features of BookE
+processors:
+
+4 hardware breakpoints (IAC)
+2 hardware watchpoints (read, write and read-write) (DAC)
+2 value conditions for the hardware watchpoints (DVC)
+
+For that, we need to extend ptrace so that GDB can query and set these
+resources. Since we're extending, we're trying to create an interface
+that's extendable and that covers both BookE and server processors, so
+that GDB doesn't need to special-case each of them. We added the
+following 3 new ptrace requests.
+
+1. PTRACE_PPC_GETHWDEBUGINFO
+
+Query for GDB to discover the hardware debug features. The main info to
+be returned here is the minimum alignment for the hardware watchpoints.
+BookE processors don't have restrictions here, but server processors have
+an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid
+adding special cases to GDB based on what it sees in AUXV.
+
+Since we're at it, we added other useful info that the kernel can return to
+GDB: this query will return the number of hardware breakpoints, hardware
+watchpoints and whether it supports a range of addresses and a condition.
+The query will fill the following structure provided by the requesting process:
+
+struct ppc_debug_info {
+       unit32_t version;
+       unit32_t num_instruction_bps;
+       unit32_t num_data_bps;
+       unit32_t num_condition_regs;
+       unit32_t data_bp_alignment;
+       unit32_t sizeof_condition; /* size of the DVC register */
+       uint64_t features; /* bitmask of the individual flags */
+};
+
+features will have bits indicating whether there is support for:
+
+#define PPC_DEBUG_FEATURE_INSN_BP_RANGE		0x1
+#define PPC_DEBUG_FEATURE_INSN_BP_MASK		0x2
+#define PPC_DEBUG_FEATURE_DATA_BP_RANGE		0x4
+#define PPC_DEBUG_FEATURE_DATA_BP_MASK		0x8
+
+2. PTRACE_SETHWDEBUG
+
+Sets a hardware breakpoint or watchpoint, according to the provided structure:
+
+struct ppc_hw_breakpoint {
+        uint32_t version;
+#define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x1
+#define PPC_BREAKPOINT_TRIGGER_READ     0x2
+#define PPC_BREAKPOINT_TRIGGER_WRITE    0x4
+        uint32_t trigger_type;       /* only some combinations allowed */
+#define PPC_BREAKPOINT_MODE_EXACT               0x0
+#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE     0x1
+#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE     0x2
+#define PPC_BREAKPOINT_MODE_MASK                0x3
+        uint32_t addr_mode;          /* address match mode */
+
+#define PPC_BREAKPOINT_CONDITION_MODE   0x3
+#define PPC_BREAKPOINT_CONDITION_NONE   0x0
+#define PPC_BREAKPOINT_CONDITION_AND    0x1
+#define PPC_BREAKPOINT_CONDITION_EXACT  0x1	/* different name for the same thing as above */
+#define PPC_BREAKPOINT_CONDITION_OR     0x2
+#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
+#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000	/* byte enable bits */
+#define PPC_BREAKPOINT_CONDITION_BE(n)  (1<<((n)+16))
+        uint32_t condition_mode;     /* break/watchpoint condition flags */
+
+        uint64_t addr;
+        uint64_t addr2;
+        uint64_t condition_value;
+};
+
+A request specifies one event, not necessarily just one register to be set.
+For instance, if the request is for a watchpoint with a condition, both the
+DAC and DVC registers will be set in the same request.
+
+With this GDB can ask for all kinds of hardware breakpoints and watchpoints
+that the BookE supports. COMEFROM breakpoints available in server processors
+are not contemplated, but that is out of the scope of this work.
+
+ptrace will return an integer (handle) uniquely identifying the breakpoint or
+watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG
+request to ask for its removal. Return -ENOSPC if the requested breakpoint
+can't be allocated on the registers.
+
+Some examples of using the structure to:
+
+- set a breakpoint in the first breakpoint register
+
+  p.version         = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+  p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;
+  p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;
+  p.addr            = (uint64_t) address;
+  p.addr2           = 0;
+  p.condition_value = 0;
+
+- set a watchpoint which triggers on reads in the second watchpoint register
+
+  p.version         = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_READ;
+  p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;
+  p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;
+  p.addr            = (uint64_t) address;
+  p.addr2           = 0;
+  p.condition_value = 0;
+
+- set a watchpoint which triggers only with a specific value
+
+  p.version         = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_READ;
+  p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;
+  p.condition_mode  = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL;
+  p.addr            = (uint64_t) address;
+  p.addr2           = 0;
+  p.condition_value = (uint64_t) condition;
+
+- set a ranged hardware breakpoint
+
+  p.version         = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+  p.addr_mode       = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+  p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;
+  p.addr            = (uint64_t) begin_range;
+  p.addr2           = (uint64_t) end_range;
+  p.condition_value = 0;
+
+3. PTRACE_DELHWDEBUG
+
+Takes an integer which identifies an existing breakpoint or watchpoint
+(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the
+corresponding breakpoint or watchpoint..

arch/powerpc/Kconfig

View file

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 50c9af4..155d571 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -58,7 +58,7 @@ config IRQ_PER_CPU
 
 config NR_IRQS
 	int "Number of virtual interrupt numbers"
-	range 32 512
+	range 32 32768
 	default "512"
 	help
 	  This defines the number of virtual interrupt numbers the kernel
@@ -241,6 +241,33 @@ config PPC_OF_PLATFORM_PCI
 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 	def_bool y
 
+config PPC_ADV_DEBUG_REGS
+	bool
+	depends on 40x || BOOKE
+	default y
+
+config PPC_ADV_DEBUG_IACS
+	int
+	depends on PPC_ADV_DEBUG_REGS
+	default 4 if 44x
+	default 2
+
+config PPC_ADV_DEBUG_DACS
+	int
+	depends on PPC_ADV_DEBUG_REGS
+	default 2
+
+config PPC_ADV_DEBUG_DVCS
+	int
+	depends on PPC_ADV_DEBUG_REGS
+	default 2 if 44x
+	default 0
+
+config PPC_ADV_DEBUG_DAC_RANGE
+	bool
+	depends on PPC_ADV_DEBUG_REGS && 44x
+	default y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"

arch/powerpc/boot/dts/arches.dts

View file

diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index 414ef8b..30f4120 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -60,6 +60,7 @@
 			d-cache-size = <32768>;
 			dcr-controller;
 			dcr-access-method = "native";
+			next-level-cache = <&L2C0>;
 		};
 	};
 
@@ -146,6 +147,13 @@
 			dcr-reg = <0x010 0x002>;
 		};
 
+		CRYPTO: crypto@180000 {
+			compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
+			reg = <4 0x00180000 0x80400>;
+			interrupt-parent = <&UIC0>;
+			interrupts = <0x1d 0x4>;
+		};
+
 		MAL0: mcmal {
 			compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
 			dcr-reg = <0x180 0x062>;
@@ -274,6 +282,7 @@
 				max-frame-size = <9000>;
 				rx-fifo-size = <4096>;
 				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
 				phy-mode = "sgmii";
 				phy-map = <0xffffffff>;
 				gpcs-address = <0x0000000a>;
@@ -302,6 +311,7 @@
 				max-frame-size = <9000>;
 				rx-fifo-size = <4096>;
 				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
 				phy-mode = "sgmii";
 				phy-map = <0x00000000>;
 				gpcs-address = <0x0000000b>;
@@ -331,6 +341,8 @@
 				max-frame-size = <9000>;
 				rx-fifo-size = <4096>;
 				tx-fifo-size = <2048>;
+				rx-fifo-size-gige = <16384>;
+				tx-fifo-size-gige = <16384>; /* emac2&3 only */
 				phy-mode = "sgmii";
 				phy-map = <0x00000001>;
 				gpcs-address = <0x0000000C>;

arch/powerpc/boot/dts/gef_ppc9a.dts

View file

diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index c86114e..977f260 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -341,6 +341,22 @@
 			device_type = "open-pic";
 		};
 
+		msi@41600 {
+			compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
+			reg = <0x41600 0x80>;
+			msi-available-ranges = <0 0x100>;
+			interrupts = <
+				0xe0 0
+				0xe1 0
+				0xe2 0
+				0xe3 0
+				0xe4 0
+				0xe5 0
+				0xe6 0
+				0xe7 0>;
+			interrupt-parent = <&mpic>;
+		};
+
 		global-utilities@e0000 {
 			compatible = "fsl,mpc8641-guts";
 			reg = <0xe0000 0x1000>;

arch/powerpc/boot/dts/gef_sbc310.dts

View file

diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 820c2b3..8e4efff 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -32,6 +32,7 @@
 		serial0 = &serial0;
 		serial1 = &serial1;
 		pci0 = &pci0;
+		pci1 = &pci1;
 	};
 
 	cpus {
@@ -338,6 +339,22 @@
 			device_type = "open-pic";
 		};
 
+		msi@41600 {
+			compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
+			reg = <0x41600 0x80>;
+			msi-available-ranges = <0 0x100>;
+			interrupts = <
+				0xe0 0
+				0xe1 0
+				0xe2 0
+				0xe3 0
+				0xe4 0
+				0xe5 0
+				0xe6 0
+				0xe7 0>;
+			interrupt-parent = <&mpic>;
+		};
+
 		global-utilities@e0000 {
 			compatible = "fsl,mpc8641-guts";
 			reg = <0xe0000 0x1000>;
@@ -358,7 +375,7 @@
 		clock-frequency = <33333333>;
 		interrupt-parent = <&mpic>;
 		interrupts = <0x18 0x2>;
-		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 		interrupt-map = <
 			0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
 			0x0000 0x0 0x0 0x2 &mpic 0x1 0x2

arch/powerpc/boot/dts/gef_sbc610.dts

View file

diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 30911ad..bb70600 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -75,14 +75,48 @@
 		interrupts = <19 2>;
 		interrupt-parent = <&mpic>;
 
-		ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
-			  1 0 0xe8000000 0x08000000     // Paged Flash 0
-			  2 0 0xe0000000 0x08000000     // Paged Flash 1
-			  3 0 0xfc100000 0x00020000     // NVRAM
-			  4 0 0xfc000000 0x00008000     // FPGA
-			  5 0 0xfc008000 0x00008000     // AFIX FPGA
-			  6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
-			  7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
+		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
+			  1 0 0xe8000000 0x08000000	// Paged Flash 0
+			  2 0 0xe0000000 0x08000000	// Paged Flash 1
+			  3 0 0xfc100000 0x00020000	// NVRAM
+			  4 0 0xfc000000 0x00008000	// FPGA
+			  5 0 0xfc008000 0x00008000	// AFIX FPGA
+			  6 0 0xfd000000 0x00800000	// IO FPGA (8-bit)
+			  7 0 0xfd800000 0x00800000>;	// IO FPGA (32-bit)
+
+		/* flash@0,0 is a mirror of part of the memory in flash@1,0
+		flash@0,0 {
+			compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
+			reg = <0x0 0x0 0x1000000>;
+			bank-width = <4>;
+			device-width = <2>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "firmware";
+				reg = <0x0 0x1000000>;
+				read-only;
+			};
+		};
+		*/
+
+		flash@1,0 {
+			compatible = "gef,sbc610-paged-flash", "cfi-flash";
+			reg = <0x1 0x0 0x8000000>;
+			bank-width = <4>;
+			device-width = <2>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "user";
+				reg = <0x0 0x7800000>;
+			};
+			partition@7800000 {
+				label = "firmware";
+				reg = <0x7800000 0x800000>;
+				read-only;
+			};
+		};
 
 		nvram@3,0 {
 			device_type = "nvram";
@@ -305,6 +339,22 @@
 			device_type = "open-pic";
 		};
 
+		msi@41600 {
+			compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
+			reg = <0x41600 0x80>;
+			msi-available-ranges = <0 0x100>;
+			interrupts = <
+				0xe0 0
+				0xe1 0
+				0xe2 0
+				0xe3 0
+				0xe4 0
+				0xe5 0
+				0xe6 0
+				0xe7 0>;
+			interrupt-parent = <&mpic>;
+		};
+
 		global-utilities@e0000 {
 			compatible = "fsl,mpc8641-guts";
 			reg = <0xe0000 0x1000>;

arch/powerpc/boot/dts/glacier.dts

View file

diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index f6f6189..d62a4fb 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for AMCC Glacier (460GT)
  *
- * Copyright 2008 DENX Software Engineering, Stefan Roese <[email protected]>
+ * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <[email protected]>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without
@@ -42,6 +42,7 @@
 			d-cache-size = <32768>;
 			dcr-controller;
 			dcr-access-method = "native";
+			next-level-cache = <&L2C0>;
 		};
 	};
 
@@ -106,6 +107,16 @@
 		dcr-reg = <0x00c 0x002>;
 	};
 
+	L2C0: l2c {
+		compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
+		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
+			   0x030 0x008>;	/* L2 cache DCR's */
+		cache-line-size = <32>;		/* 32 bytes */
+		cache-size = <262144>;		/* L2, 256K */
+		interrupt-parent = <&UIC1>;
+		interrupts = <11 1>;
+	};
+
 	plb {
 		compatible = "ibm,plb-460gt", "ibm,plb4";
 		#address-cells = <2>;
@@ -118,6 +129,13 @@
 			dcr-reg = <0x010 0x002>;
 		};
 
+		CRYPTO: crypto@180000 {
+			compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
+			reg = <4 0x00180000 0x80400>;
+			interrupt-parent = <&UIC0>;
+			interrupts = <0x1d 0x4>;
+		};
+
 		MAL0: mcmal {
 			compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
 			dcr-reg = <0x180 0x062>;
@@ -186,6 +204,29 @@
 						reg = <0x03fa0000 0x00060000>;
 					};
 				};
+
+				ndfc@3,0 {
+					compatible = "ibm,ndfc";
+					reg = <0x00000003 0x00000000 0x00002000>;
+					ccr = <0x00001000>;
+					bank-settings = <0x80002222>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					nand {
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						partition@0 {
+							label = "u-boot";
+							reg = <0x00000000 0x00100000>;
+						};
+						partition@100000 {
+							label = "user";
+							reg = <0x00000000 0x03f00000>;
+						};
+					};
+				};
 			};
 
 			UART0: serial@ef600300 {
@@ -237,6 +278,20 @@
 				reg = <0xef600700 0x00000014>;
 				interrupt-parent = <&UIC0>;
 				interrupts = <0x2 0x4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				rtc@68 {
+					compatible = "stm,m41t80";
+					reg = <0x68>;
+					interrupt-parent = <&UIC2>;
+					interrupts = <0x19 0x8>;
+				};
+				sttm@48 {
+					compatible = "ad,ad7414";
+					reg = <0x48>;
+					interrupt-parent = <&UIC1>;
+					interrupts = <0x14 0x8>;
+				};
 			};
 
 			IIC1: i2c@ef600800 {
@@ -275,7 +330,7 @@
 
 			EMAC0: ethernet@ef600e00 {
 				device_type = "network";
-				compatible = "ibm,emac-460gt", "ibm,emac4";