Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

f4a6365a · Linus Torvalds <[email protected]> · 2020-02-03 22:10:18 +00:00

Pull clk updates from Stephen Boyd:
 "There are a few changes to the core framework this time around, in
  addition to the normal collection of driver updates to support new
  SoCs, fix incorrect data, and convert various drivers to clk_hw based
  APIs.

  In the core, we allow clk_ops::init() to return an error code now so
  that we can fail clk registration if the callback does something like
  fail to allocate memory. We also add a new "terminate" clk_op so that
  things done in clk_ops::init() can be undone, e.g. free memory. We
  also spit out a warning now when critical clks fail to enable and we
  support changing clk rates and enable/disable state through debugfs
  when developers compile the kernel themselves.

  On the driver front, we get support for what seems like a lot of
  Qualcomm and NXP SoCs given that those vendors dominate the diffstat.
  There are a couple new drivers for Xilinx and Amlogic SoCs too. The
  updates are all small things like fixing the way glitch free muxes
  switch parents, avoiding div-by-zero problems, or fixing data like
  parent names. See the updates section below for more details.

  Finally, the "basic" clk types have been converted to support
  specifying parents with clk_hw pointers. This work includes an
  overhaul of the fixed-rate clk type to be more modern by using clk_hw
  APIs.

  Core:
   - Let clk_ops::init() return an error code
   - Add a clk_ops::terminate() callback to undo clk_ops::init()
   - Warn about critical clks that fail to enable or prepare
   - Support dangerous debugfs actions on clks with dead code

  New Drivers:
   - Support for Xilinx Versal platform clks
   - Display clk controller on qcom sc7180
   - Video clk controller on qcom sc7180
   - Graphics clk controller on qcom sc7180
   - CPU PLLs for qcom msm8916
   - Move qcom msm8974 gfx3d clk to RPM control
   - Display port clk support on qcom sdm845 SoCs
   - Global clk controller on qcom ipq6018
   - Add a driver for BCLK of Freescale SAI cores
   - Add cam, vpe and sgx clock support for TI dra7
   - Add aess clock support for TI omap5
   - Enable clks for CPUfreq on Allwinner A64 SoCs
   - Add Amlogic meson8b DDR clock controller
   - Add input clocks to Amlogic meson8b controllers
   - Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2
   - i.MX8MP clk driver support

  Updates:
   - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw
     based APIs
   - Detect more PRMCU variants in ux500 driver
   - Adjust the composite clk type to new way of describing clk parents
   - Fixes for clk controllers on qcom msm8998 SoCs
   - Fix gmac main clock for TI dra7
   - Move TI dra7-atl clock header to correct location
   - Fix hidden node name dependency on TI clkctrl clocks
   - Fix Amlogic meson8b mali clock update using the glitch free mux
   - Fix Amlogic pll driver division by zero at init
   - Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config
     symbols
   - Switch more i.MX clk drivers to clk_hw based APIs
   - Disable non-functional divider between pll4_audio_div and
     pll4_post_div on imx6q
   - Fix watchdog2 clock name typo in imx7ulp clock driver
   - Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M
     SoCs
   - Suppress bind attrs for i.MX8M clock driver
   - Add a big comment in imx8qxp-lpcg driver to tell why
     devm_platform_ioremap_resource() shouldn't be used for the driver
   - A correction on i.MX8MN usb1_ctrl parent clock setting"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (140 commits)
  dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema id
  clk: ls1028a: Fix warning on clamp() usage
  clk: qoriq: add ls1088a hwaccel clocks support
  clk: ls1028a: Add clock driver for Display output interface
  dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
  clk: fsl-sai: new driver
  dt-bindings: clock: document the fsl-sai driver
  clk: composite: add _register_composite_pdata() variants
  clk: qcom: rpmh: Sort OF match table
  dt-bindings: fix warnings in validation of qcom,gcc.yaml
  dt-binding: fix compilation error of the example in qcom,gcc.yaml
  clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
  clk: zynqmp: Fix divider calculation
  clk: zynqmp: Add support for get max divider
  clk: zynqmp: Warn user if clock user are more than allowed
  clk: zynqmp: Extend driver for versal
  dt-bindings: clock: Add bindings for versal clock driver
  clk: ti: clkctrl: Fix hidden dependency to node name
  clk: ti: add clkctrl data dra7 sgx
  clk: ti: omap5: Add missing AESS clock
  ...

Commit: f4a6365ae88d38528b4eec717326dab877b515ea
Parents: fe70da5a · fc6a15c8

Merge commit. Changes below are compared with the first parent: fe70da5a.

Changes

146 files changed · +15018 −1806

File	Status	Add	Del	Content
Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml	added	+50	−0	View file
Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt	modified	+5	−0	View file
Documentation/devicetree/bindings/clock/fsl,plldig.yaml	added	+54	−0	View file
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml	added	+55	−0	View file
Documentation/devicetree/bindings/clock/imx8mp-clock.yaml	added	+68	−0	View file
Documentation/devicetree/bindings/clock/qcom,dispcc.txt	deleted	+0	−19	View before deletion
Documentation/devicetree/bindings/clock/qcom,dispcc.yaml	added	+67	−0	View file
Documentation/devicetree/bindings/clock/qcom,gcc.yaml	modified	+72	−15	View file
Documentation/devicetree/bindings/clock/qcom,gpucc.txt	deleted	+0	−24	View before deletion
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml	added	+72	−0	View file
Documentation/devicetree/bindings/clock/qcom,mmcc.txt	deleted	+0	−28	View before deletion
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml	added	+98	−0	View file
Documentation/devicetree/bindings/clock/qcom,videocc.txt	deleted	+0	−18	View before deletion
Documentation/devicetree/bindings/clock/qcom,videocc.yaml	added	+62	−0	View file
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt	modified	+1	−1	View file
Documentation/devicetree/bindings/clock/ti-clkctrl.txt	modified	+8	−3	View file
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt	modified	+2	−2	View file
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml	added	+64	−0	View file
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt	modified	+21	−3	View file
arch/arm/boot/dts/dra7-evm-common.dtsi	modified	+1	−1	View file
arch/arm/boot/dts/dra72-evm-common.dtsi	modified	+1	−1	View file
arch/arm/boot/dts/dra7xx-clocks.dtsi	modified	+14	−0	View file
drivers/clk/Kconfig	modified	+23	−1	View file
drivers/clk/Makefile	modified	+2	−0	View file
drivers/clk/at91/clk-sam9x60-pll.c	modified	+6	−2	View file
drivers/clk/at91/sam9x60.c	modified	+1	−0	View file
drivers/clk/clk-asm9260.c	modified	+4	−4	View file
drivers/clk/clk-bm1880.c	modified	+1	−2	View file
drivers/clk/clk-composite.c	modified	+53	−3	View file
drivers/clk/clk-divider.c	modified	+10	−81	View file
drivers/clk/clk-fixed-rate.c	modified	+47	−66	View file
drivers/clk/clk-fsl-sai.c	added	+92	−0	View file
drivers/clk/clk-gate.c	modified	+18	−17	View file
drivers/clk/clk-gpio.c	modified	+59	−113	View file
drivers/clk/clk-mux.c	modified	+18	−40	View file
drivers/clk/clk-plldig.c	added	+286	−0	View file
drivers/clk/clk-qoriq.c	modified	+29	−0	View file
drivers/clk/clk.c	modified	+94	−16	View file
drivers/clk/imx/Kconfig	modified	+6	−0	View file
drivers/clk/imx/Makefile	modified	+2	−1	View file
drivers/clk/imx/clk-composite-7ulp.c	modified	+1	−1	View file
drivers/clk/imx/clk-composite-8m.c	modified	+2	−2	View file
drivers/clk/imx/clk-divider-gate.c	modified	+6	−6	View file
drivers/clk/imx/clk-frac-pll.c	modified	+4	−3	View file
drivers/clk/imx/clk-imx6q.c	modified	+4	−1	View file
drivers/clk/imx/clk-imx7ulp.c	modified	+91	−91	View file
drivers/clk/imx/clk-imx8mm.c	modified	+294	−271	View file
drivers/clk/imx/clk-imx8mn.c	modified	+261	−237	View file
drivers/clk/imx/clk-imx8mp.c	added	+764	−0	View file
drivers/clk/imx/clk-imx8mq.c	modified	+302	−282	View file
drivers/clk/imx/clk-imx8qxp-lpcg.c	modified	+11	−0	View file
drivers/clk/imx/clk-pfdv2.c	modified	+1	−1	View file
drivers/clk/imx/clk-pll14xx.c	modified	+20	−9	View file
drivers/clk/imx/clk-pllv1.c	modified	+9	−5	View file
drivers/clk/imx/clk-pllv2.c	modified	+9	−5	View file
drivers/clk/imx/clk-pllv4.c	modified	+1	−1	View file
drivers/clk/imx/clk-sccg-pll.c → drivers/clk/imx/clk-sscg-pll.c	renamed	+76	−76	View file
drivers/clk/imx/clk.c	modified	+10	−2	View file
drivers/clk/imx/clk.h	modified	+104	−58	View file
drivers/clk/mediatek/Kconfig	modified	+22	−22	View file
drivers/clk/meson/Makefile	modified	+1	−1	View file
drivers/clk/meson/clk-mpll.c	modified	+3	−1	View file
drivers/clk/meson/clk-phase.c	modified	+3	−1	View file
drivers/clk/meson/clk-pll.c	modified	+12	−1	View file
drivers/clk/meson/g12a.c	modified	+1	−0	View file
drivers/clk/meson/meson8-ddr.c	added	+149	−0	View file
drivers/clk/meson/meson8b.c	modified	+69	−55	View file
drivers/clk/meson/sclk-div.c	modified	+3	−1	View file
drivers/clk/microchip/clk-core.c	modified	+6	−2	View file
drivers/clk/mmp/clk-frac.c	modified	+3	−1	View file
drivers/clk/mmp/clk-mix.c	modified	+3	−1	View file
drivers/clk/mvebu/Kconfig	modified	+1	−1	View file
drivers/clk/qcom/Kconfig	modified	+45	−2	View file
drivers/clk/qcom/Makefile	modified	+5	−0	View file
drivers/clk/qcom/apcs-msm8916.c	modified	+7	−6	View file
drivers/clk/qcom/clk-alpha-pll.c	modified	+85	−6	View file
drivers/clk/qcom/clk-alpha-pll.h	modified	+5	−0	View file
drivers/clk/qcom/clk-hfpll.c	modified	+4	−2	View file
drivers/clk/qcom/clk-rcg.h	modified	+1	−0	View file
drivers/clk/qcom/clk-rcg2.c	modified	+77	−0	View file
drivers/clk/qcom/clk-rpmh.c	modified	+8	−2	View file
drivers/clk/qcom/clk-smd-rpm.c	modified	+5	−0	View file
drivers/clk/qcom/dispcc-sc7180.c	added	+776	−0	View file
drivers/clk/qcom/dispcc-sdm845.c	modified	+213	−1	View file
drivers/clk/qcom/gcc-ipq6018.c	added	+4635	−0	View file
drivers/clk/qcom/gcc-msm8996.c	modified	+28	−7	View file
drivers/clk/qcom/gcc-msm8998.c	modified	+14	−0	View file
drivers/clk/qcom/gcc-qcs404.c	modified	+1	−1	View file
drivers/clk/qcom/gpucc-sc7180.c	added	+266	−0	View file
drivers/clk/qcom/hfpll.c	modified	+19	−2	View file
drivers/clk/qcom/mmcc-msm8974.c	modified	+0	−13	View file
drivers/clk/qcom/mmcc-msm8998.c	added	+2913	−0	View file
drivers/clk/qcom/videocc-sc7180.c	added	+259	−0	View file
drivers/clk/renesas/Kconfig	modified	+2	−2	View file
drivers/clk/renesas/r7s9210-cpg-mssr.c	modified	+1	−0	View file
drivers/clk/renesas/rcar-gen2-cpg.h	modified	+4	−4	View file
drivers/clk/renesas/rcar-gen3-cpg.c	modified	+4	−2	View file
drivers/clk/rockchip/clk-pll.c	modified	+17	−11	View file
drivers/clk/sunxi-ng/ccu-sun50i-a64.c	modified	+27	−1	View file
drivers/clk/sunxi-ng/ccu-sun50i-a64.h	modified	+0	−1	View file
drivers/clk/sunxi-ng/ccu-sun6i-a31.h	modified	+3	−1	View file
drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h	modified	+3	−1	View file
drivers/clk/sunxi-ng/ccu-sun8i-r40.h	modified	+0	−4	View file
drivers/clk/sunxi/clk-sun6i-apb0-gates.c	modified	+2	−4	View file
drivers/clk/tegra/clk-dfll.c	modified	+1	−2	View file
drivers/clk/tegra/clk-divider.c	modified	+7	−2	View file
drivers/clk/tegra/clk-tegra-periph.c	modified	+5	−1	View file
drivers/clk/tegra/clk-tegra20.c	modified	+1	−3	View file
drivers/clk/tegra/clk-tegra30.c	modified	+1	−3	View file
drivers/clk/ti/clk-54xx.c	modified	+15	−0	View file
drivers/clk/ti/clk-7xx.c	modified	+61	−1	View file
drivers/clk/ti/clk.c	modified	+3	−1	View file
drivers/clk/ti/clkctrl.c	modified	+85	−11	View file
drivers/clk/ti/clock.h	modified	+1	−1	View file
drivers/clk/ti/clockdomain.c	modified	+5	−3	View file
drivers/clk/uniphier/clk-uniphier-peri.c	modified	+8	−5	View file
drivers/clk/ux500/u8500_of_clk.c	modified	+2	−0	View file
drivers/clk/versatile/Kconfig	modified	+1	−1	View file
drivers/clk/zynqmp/clkc.c	modified	+2	−1	View file
drivers/clk/zynqmp/divider.c	modified	+113	−5	View file
drivers/clk/zynqmp/pll.c	modified	+4	−2	View file
drivers/firmware/xilinx/zynqmp.c	modified	+2	−0	View file
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c	modified	+2	−2	View file
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c	modified	+2	−2	View file
drivers/net/phy/mdio-mux-meson-g12a.c	modified	+3	−1	View file
include/dt-bindings/clock/dra7.h	modified	+23	−0	View file
include/dt-bindings/clock/imx8mp-clock.h	added	+300	−0	View file
include/dt-bindings/clock/meson8-ddr-clkc.h	added	+4	−0	View file
include/dt-bindings/clock/omap5.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,dispcc-sc7180.h	added	+46	−0	View file
include/dt-bindings/clock/qcom,dispcc-sdm845.h	modified	+12	−1	View file
include/dt-bindings/clock/qcom,gcc-ipq6018.h	added	+262	−0	View file
include/dt-bindings/clock/qcom,gcc-msm8998.h	modified	+1	−0	View file
include/dt-bindings/clock/qcom,gpucc-sc7180.h	added	+21	−0	View file
include/dt-bindings/clock/qcom,mmcc-msm8998.h	added	+210	−0	View file
include/dt-bindings/clock/qcom,videocc-sc7180.h	added	+23	−0	View file
include/dt-bindings/clock/sun50i-a64-ccu.h	modified	+1	−0	View file
include/dt-bindings/clock/sun6i-a31-ccu.h	modified	+2	−0	View file
include/dt-bindings/clock/sun8i-a23-a33-ccu.h	modified	+2	−0	View file
include/dt-bindings/clock/sun8i-r40-ccu.h	modified	+1	−1	View file
include/dt-bindings/clk/ti-dra7-atl.h → include/dt-bindings/clock/ti-dra7-atl.h	renamed	+0	−0	View file
include/dt-bindings/clock/xlnx-versal-clk.h	added	+123	−0	View file
include/dt-bindings/reset/qcom,gcc-ipq6018.h	added	+157	−0	View file
include/linux/clk-provider.h	modified	+359	−85	View file
include/linux/clk.h	modified	+3	−0	View file
include/linux/firmware/xlnx-zynqmp.h	modified	+2	−0	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml

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diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
new file mode 100644
index 0000000..4b8669f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic DDR Clock Controller Device Tree Bindings
+
+maintainers:
+  - Martin Blumenstingl <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - amlogic,meson8-ddr-clkc
+      - amlogic,meson8b-ddr-clkc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: xtal
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    ddr_clkc: clock-controller@400 {
+      compatible = "amlogic,meson8-ddr-clkc";
+      reg = <0x400 0x20>;
+      clocks = <&xtal>;
+      clock-names = "xtal";
+      #clock-cells = <1>;
+    };
+
+...

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

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diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 4d94091..cc51e47 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -11,6 +11,11 @@ Required Properties:
 	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
+- clocks: list of clock phandles, one for each entry in clock-names
+- clock-names: should contain the following:
+  * "xtal": the 24MHz system oscillator
+  * "ddr_pll": the DDR PLL clock
+  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
 
 Parent node should have the following properties :
 - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

Documentation/devicetree/bindings/clock/fsl,plldig.yaml

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diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
new file mode 100644
index 0000000..c835003
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
+
+maintainers:
+  - Wen He <[email protected]>
+
+description: |
+  NXP LS1028A has a clock domain PXLCLK0 used for the Display output
+  interface in the display core, as implemented in TSMC CLN28HPM PLL.
+  which generate and offers pixel clocks to Display.
+
+properties:
+  compatible:
+    const: fsl,ls1028a-plldig
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+  fsl,vco-hz:
+     description: Optional for VCO frequency of the PLL in Hertz.
+        The VCO frequency of this PLL cannot be changed during runtime
+        only at startup. Therefore, the output frequencies are very
+        limited and might not even closely match the requested frequency.
+        To work around this restriction the user may specify its own
+        desired VCO frequency for the PLL.
+     minimum: 650000000
+     maximum: 1300000000
+     default: 1188000000
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+examples:
+  # Display PIXEL Clock node:
+  - |
+    dpclk: clock-display@f1f0000 {
+        compatible = "fsl,ls1028a-plldig";
+        reg = <0x0 0xf1f0000 0x0 0xffff>;
+        #clock-cells = <0>;
+        clocks = <&osc_27m>;
+    };
+
+...

Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
new file mode 100644
index 0000000..8fb2060
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/fsl,sai-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SAI bitclock-as-a-clock binding
+
+maintainers:
+  - Michael Walle <[email protected]>
+
+description: |
+  It is possible to use the BCLK pin of a SAI module as a generic clock
+  output. Some SoC are very constrained in their pin multiplexer
+  configuration. Eg. pins can only be changed groups. For example, on the
+  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
+  the second pins are wasted. Using this binding it is possible to use the
+  clock of the second SAI as a MCLK clock for an audio codec, for example.
+
+  This is a composite of a gated clock and a divider clock.
+
+properties:
+  compatible:
+    const: fsl,vf610-sai-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mclk: clock-mclk@f130080 {
+            compatible = "fsl,vf610-sai-clock";
+            reg = <0x0 0xf130080 0x0 0x80>;
+            #clock-cells = <0>;
+            clocks = <&parentclk>;
+        };
+    };

Documentation/devicetree/bindings/clock/imx8mp-clock.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml
new file mode 100644
index 0000000..8027888
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/imx8mp-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Plus Clock Control Module Binding
+
+maintainers:
+  - Anson Huang <[email protected]>
+
+description:
+  NXP i.MX8M Plus clock control module is an integrated clock controller, which
+  generates and supplies to all modules.
+
+properties:
+  compatible:
+    const: fsl,imx8mp-ccm
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: 32k osc
+      - description: 24m osc
+      - description: ext1 clock input
+      - description: ext2 clock input
+      - description: ext3 clock input
+      - description: ext4 clock input
+
+  clock-names:
+    items:
+      - const: osc_32k
+      - const: osc_24m
+      - const: clk_ext1
+      - const: clk_ext2
+      - const: clk_ext3
+      - const: clk_ext4
+
+  '#clock-cells':
+    const: 1
+    description:
+      The clock consumer should specify the desired clock by having the clock
+      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
+      for the full list of i.MX8M Plus clock IDs.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+examples:
+  # Clock Control Module node:
+  - |
+    clk: clock-controller@30380000 {
+        compatible = "fsl,imx8mp-ccm";
+        reg = <0x30380000 0x10000>;
+        #clock-cells = <1>;
+        clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
+                 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
+        clock-names = "osc_32k", "osc_24m", "clk_ext1",
+                      "clk_ext2", "clk_ext3", "clk_ext4";
+    };
+
+...

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

View before deletion

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
deleted file mode 100644
index d639e18..0000000
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Qualcomm Technologies, Inc. Display Clock Controller Binding
-------------------------------------------------------------
-
-Required properties :
-
-- compatible : shall contain "qcom,sdm845-dispcc"
-- reg : shall contain base register location and length.
-- #clock-cells : from common clock binding, shall contain 1.
-- #reset-cells : from common reset binding, shall contain 1.
-- #power-domain-cells : from generic power domain binding, shall contain 1.
-
-Example:
-	dispcc: clock-controller@af00000 {
-		compatible = "qcom,sdm845-dispcc";
-		reg = <0xaf00000 0x100000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-		#power-domain-cells = <1>;
-	};

Documentation/devicetree/bindings/clock/qcom,dispcc.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
new file mode 100644
index 0000000..9c58e02
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/qcom,dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding
+
+maintainers:
+  - Taniya Das <[email protected]>
+
+description: |
+  Qualcomm display clock control module which supports the clocks, resets and
+  power domains.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sc7180-dispcc
+      - qcom,sdm845-dispcc
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: Board XO source
+      - description: GPLL0 source from GCC
+
+  clock-names:
+    items:
+      - const: xo
+      - const: gpll0
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+examples:
+  # Example of DISPCC with clock node properties for SDM845:
+  - |
+    clock-controller@af00000 {
+      compatible = "qcom,sdm845-dispcc";
+      reg = <0xaf00000 0x10000>;
+      clocks = <&rpmhcc 0>, <&gcc 24>;
+      clock-names = "xo", "gpll0";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+     };
+...

Documentation/devicetree/bindings/clock/qcom,gcc.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index e73a56f..cac1150 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -19,8 +19,9 @@ properties:
     enum:
        - qcom,gcc-apq8064
        - qcom,gcc-apq8084
-       - qcom,gcc-ipq8064
        - qcom,gcc-ipq4019
+       - qcom,gcc-ipq6018
+       - qcom,gcc-ipq8064
        - qcom,gcc-ipq8074
        - qcom,gcc-msm8660
        - qcom,gcc-msm8916
@@ -40,20 +41,50 @@ properties:
        - qcom,gcc-sm8150
 
   clocks:
-    minItems: 1
-    maxItems: 3
-    items:
-      - description: Board XO source
-      - description: Board active XO source
-      - description: Sleep clock source
+    oneOf:
+      #qcom,gcc-sm8150
+      #qcom,gcc-sc7180
+      - items:
+        - description: Board XO source
+        - description: Board active XO source
+        - description: Sleep clock source
+      #qcom,gcc-msm8996
+      - items:
+        - description: XO source
+        - description: Second XO source
+        - description: Sleep clock source
+      #qcom,gcc-msm8998
+      - items:
+        - description: Board XO source
+        - description: Sleep clock source
+        - description: USB 3.0 phy pipe clock
+        - description: UFS phy rx symbol clock for pipe 0
+        - description: UFS phy rx symbol clock for pipe 1
+        - description: UFS phy tx symbol clock
+        - description: PCIE phy pipe clock
 
   clock-names:
-    minItems: 1
-    maxItems: 3
-    items:
-      - const: bi_tcxo
-      - const: bi_tcxo_ao
-      - const: sleep_clk
+    oneOf:
+      #qcom,gcc-sm8150
+      #qcom,gcc-sc7180
+      - items:
+        - const: bi_tcxo
+        - const: bi_tcxo_ao
+        - const: sleep_clk
+      #qcom,gcc-msm8996
+      - items:
+        - const: cxo
+        - const: cxo2
+        - const: sleep_clk
+      #qcom,gcc-msm8998
+      - items:
+        - const: xo
+        - const: sleep_clk
+        - const: usb3_pipe
+        - const: ufs_rx_symbol0
+        - const: ufs_rx_symbol1
+        - const: ufs_tx_symbol0
+        - const: pcie0_pipe
 
   '#clock-cells':
     const: 1
@@ -118,6 +149,7 @@ else:
       compatible:
         contains:
           enum:
+            - qcom,gcc-msm8998
             - qcom,gcc-sm8150
             - qcom,gcc-sc7180
   then:
@@ -179,10 +211,35 @@ examples:
     clock-controller@100000 {
       compatible = "qcom,gcc-sc7180";
       reg = <0x100000 0x1f0000>;
-      clocks = <&rpmhcc 0>, <&rpmhcc 1>;
-      clock-names = "bi_tcxo", "bi_tcxo_ao";
+      clocks = <&rpmhcc 0>, <&rpmhcc 1>, <0>;
+      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+
+  # Example of MSM8998 GCC:
+  - |
+    #include <dt-bindings/clock/qcom,rpmcc.h>
+    clock-controller@100000 {
+      compatible = "qcom,gcc-msm8998";
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;
+      reg = <0x00100000 0xb0000>;
+      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+               <&sleep>,
+               <0>,
+               <0>,
+               <0>,
+               <0>,
+               <0>;
+      clock-names = "xo",
+                    "sleep_clk",
+                    "usb3_pipe",
+                    "ufs_rx_symbol0",
+                    "ufs_rx_symbol1",
+                    "ufs_tx_symbol0",
+                    "pcie0_pipe";
     };
 ...

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

View before deletion

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
deleted file mode 100644
index 269afe8..0000000
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Qualcomm Graphics Clock & Reset Controller Binding
---------------------------------------------------
-
-Required properties :
-- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
-- reg : shall contain base register location and length
-- #clock-cells : from common clock binding, shall contain 1
-- #reset-cells : from common reset binding, shall contain 1
-- #power-domain-cells : from generic power domain binding, shall contain 1
-- clocks : shall contain the XO clock
-	   shall contain the gpll0 out main clock (msm8998)
-- clock-names : shall be "xo"
-		shall be "gpll0" (msm8998)
-
-Example:
-	gpucc: clock-controller@5090000 {
-		compatible = "qcom,sdm845-gpucc";
-		reg = <0x5090000 0x9000>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-		#power-domain-cells = <1>;
-		clocks = <&rpmhcc RPMH_CXO_CLK>;
-		clock-names = "xo";
-	};

Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

View file

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
new file mode 100644
index 0000000..622845a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding
+
+maintainers:
+  - Taniya Das <[email protected]>
+
+description: |
+  Qualcomm grpahics clock control module which supports the clocks, resets and
+  power domains.
+
+properties:
+  compatible:
+    enum:
+      - qcom,msm8998-gpucc
+      - qcom,sc7180-gpucc
+      - qcom,sdm845-gpucc
+
+  clocks:
+    minItems: 1
+    maxItems: 3
+    items:
+      - description: Board XO source
+      - description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)
+      - description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)
+
+  clock-names:
+    minItems: 1
+    maxItems: 3
+    items:
+      - const: xo
+      - const: gpll0_main
+      - const: gpll0_div
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+examples:
+  # Example of GPUCC with clock node properties for SDM845:
+  - |
+    clock-controller@5090000 {
+      compatible = "qcom,sdm845-gpucc";
+      reg = <0x5090000 0x9000>;
+      clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;
+      clock-names = "xo", "gpll0_main", "gpll0_div";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+     };
+...

Documentation/devicetree/bindings/clock/qcom,mmcc.txt

View before deletion

diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
deleted file mode 100644
index 8b0f784..0000000

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