Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm

ff8ce5f6 · Linus Torvalds <[email protected]> · 2012-05-21 16:01:50 -07:00

Pull core ARM updates from Russell King:
 "This is the bulk of the core ARM updates for this merge window.
  Included in here is a different way to handle the VIVT cache flushing
  on context switch, which should allow scheduler folk to remove a
  special case in their core code.

  We have architectured timer support here, which is a set of timers
  specified by the ARM architecture for future SoCs.  So we should see
  less variability in timer design going forward.

  The last big thing here is my cleanup to the way we handle PCI across
  ARM, fixing some oddities in some platforms which hadn't realised
  there was a way to deal with their private data already built in to
  our PCI backend.

  I've also removed support for the ARMv3 architecture; it hasn't worked
  properly for years so it seems pointless to keep it around."

* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (47 commits)
  ARM: PCI: remove per-pci_hw list of buses
  ARM: PCI: dove/kirkwood/mv78xx0: use sys->private_data
  ARM: PCI: provide a default bus scan implementation
  ARM: PCI: get rid of pci_std_swizzle()
  ARM: PCI: versatile: fix PCI interrupt setup
  ARM: PCI: integrator: use common PCI swizzle
  ARM: 7416/1: LPAE: Remove unused L_PTE_(BUFFERABLE|CACHEABLE) macros
  ARM: 7415/1: vfp: convert printk's to pr_*'s
  ARM: decompressor: avoid speculative prefetch from non-RAM areas
  ARM: Remove ARMv3 support from decompressor
  ARM: 7413/1: move read_{boot,persistent}_clock to the architecture level
  ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs
  ARM: 7363/1: DEBUG_LL: limit early mapping to the minimum
  ARM: 7391/1: versatile: add some auxdata for device trees
  ARM: 7389/2: plat-versatile: modernize FPGA IRQ controller
  AMBA: get rid of last two uses of NO_IRQ
  ARM: 7408/1: cacheflush: return error to userspace when flushing syscall fails
  ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
  ARM: 7404/1: cmpxchg64: use atomic64 and local64 routines for cmpxchg64
  ARM: 7347/1: SCU: use cpu_logical_map for per-CPU low power mode
  ...

Commit: ff8ce5f67ddca709fe59e6173f89260f0fdc2b22
Parents: 4f6ade91 · 4ab10567

Merge commit. Changes below are compared with the first parent: 4f6ade91.

Changes

159 files changed · +1461 −2455

File	Status	Add	Del	Content
Documentation/devicetree/bindings/arm/arch_timer.txt	added	+27	−0	View file
arch/arm/Kconfig	modified	+10	−12	View file
arch/arm/Makefile	modified	+0	−2	View file
arch/arm/boot/compressed/head.S	modified	+21	−50	View file
arch/arm/common/it8152.c	modified	+1	−6	View file
arch/arm/common/via82c505.c	modified	+1	−10	View file
arch/arm/common/vic.c	modified	+31	−25	View file
arch/arm/configs/rpc_defconfig	modified	+0	−2	View file
arch/arm/include/asm/arch_timer.h	added	+19	−0	View file
arch/arm/include/asm/cacheflush.h	modified	+3	−3	View file
arch/arm/include/asm/cmpxchg.h	modified	+13	−60	View file
arch/arm/include/asm/glue-df.h	modified	+0	−8	View file
arch/arm/include/asm/glue-proc.h	modified	+0	−18	View file
arch/arm/include/asm/hardware/it8152.h	modified	+1	−1	View file
arch/arm/include/asm/mach/pci.h	modified	+6	−11	View file
arch/arm/include/asm/mach/time.h	modified	+5	−0	View file
arch/arm/include/asm/mmu.h	modified	+0	−7	View file
arch/arm/include/asm/mmu_context.h	modified	+79	−25	View file
arch/arm/include/asm/page.h	modified	+0	−9	View file
arch/arm/include/asm/pgtable-3level.h	modified	+0	−2	View file
arch/arm/include/asm/ptrace.h	modified	+5	−0	View file
arch/arm/include/asm/syscall.h	added	+93	−0	View file
arch/arm/include/asm/thread_info.h	modified	+1	−0	View file
arch/arm/include/asm/tlbflush.h	modified	+2	−19	View file
arch/arm/kernel/Makefile	modified	+1	−0	View file
arch/arm/kernel/arch_timer.c	added	+350	−0	View file
arch/arm/kernel/bios32.c	modified	+26	−11	View file
arch/arm/kernel/entry-armv.S	modified	+0	−4	View file
arch/arm/kernel/entry-common.S	modified	+0	−28	View file
arch/arm/kernel/head.S	modified	+1	−8	View file
arch/arm/kernel/ptrace.c	modified	+6	−15	View file
arch/arm/kernel/signal.c	modified	+2	−0	View file
arch/arm/kernel/smp.c	modified	+3	−0	View file
arch/arm/kernel/smp_scu.c	modified	+2	−1	View file
arch/arm/kernel/thumbee.c	modified	+2	−2	View file
arch/arm/kernel/time.c	modified	+36	−0	View file
arch/arm/kernel/traps.c	modified	+6	−5	View file
arch/arm/lib/Makefile	modified	+3	−20	View file
arch/arm/lib/io-readsw-armv3.S	deleted	+0	−106	View before deletion
arch/arm/lib/io-writesw-armv3.S	deleted	+0	−126	View before deletion
arch/arm/lib/uaccess.S	deleted	+0	−564	View before deletion
arch/arm/mach-cns3xxx/pcie.c	modified	+2	−10	View file
arch/arm/mach-dove/pcie.c	modified	+7	−17	View file
arch/arm/mach-footbridge/cats-pci.c	modified	+7	−2	View file
arch/arm/mach-footbridge/dc21285.c	modified	+1	−6	View file
arch/arm/mach-footbridge/ebsa285-pci.c	modified	+1	−2	View file
arch/arm/mach-footbridge/netwinder-pci.c	modified	+1	−2	View file
arch/arm/mach-footbridge/personal-pci.c	modified	+1	−1	View file
arch/arm/mach-integrator/impd1.c	modified	+7	−15	View file
arch/arm/mach-integrator/include/mach/entry-macro.S	deleted	+0	−39	View before deletion
arch/arm/mach-integrator/include/mach/irqs.h	modified	+31	−32	View file
arch/arm/mach-integrator/integrator_ap.c	modified	+3	−7	View file
arch/arm/mach-integrator/integrator_cp.c	modified	+10	−23	View file
arch/arm/mach-integrator/pci.c	modified	+4	−15	View file
arch/arm/mach-integrator/pci_v3.c	modified	+1	−7	View file
arch/arm/mach-iop13xx/iq81340mc.c	modified	+0	−1	View file
arch/arm/mach-iop13xx/iq81340sc.c	modified	+0	−1	View file
arch/arm/mach-iop32x/em7210.c	modified	+1	−2	View file
arch/arm/mach-iop32x/glantank.c	modified	+1	−2	View file
arch/arm/mach-iop32x/iq31244.c	modified	+2	−4	View file
arch/arm/mach-iop32x/iq80321.c	modified	+1	−2	View file
arch/arm/mach-iop32x/n2100.c	modified	+1	−2	View file
arch/arm/mach-iop33x/iq80331.c	modified	+1	−2	View file
arch/arm/mach-iop33x/iq80332.c	modified	+1	−2	View file
arch/arm/mach-ixp2000/enp2611.c	modified	+1	−8	View file
arch/arm/mach-ixp2000/include/mach/platform.h	modified	+1	−1	View file
arch/arm/mach-ixp2000/ixdp2400.c	modified	+1	−1	View file
arch/arm/mach-ixp2000/ixdp2800.c	modified	+1	−1	View file
arch/arm/mach-ixp2000/ixdp2x01.c	modified	+1	−1	View file
arch/arm/mach-ixp2000/pci.c	modified	+1	−7	View file
arch/arm/mach-ixp23xx/include/mach/platform.h	modified	+1	−1	View file
arch/arm/mach-ixp23xx/ixdp2351.c	modified	+1	−1	View file
arch/arm/mach-ixp23xx/pci.c	modified	+0	−6	View file
arch/arm/mach-ixp23xx/roadrunner.c	modified	+1	−1	View file
arch/arm/mach-ixp4xx/avila-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/common-pci.c	modified	+0	−6	View file
arch/arm/mach-ixp4xx/coyote-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/dsmg600-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/fsg-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/gateway7001-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/goramo_mlr.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/gtwx5715-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/include/mach/platform.h	modified	+1	−1	View file
arch/arm/mach-ixp4xx/ixdp425-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/ixdpg425-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/miccpt-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/nas100d-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/nslu2-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/vulcan-pci.c	modified	+1	−2	View file
arch/arm/mach-ixp4xx/wg302v2-pci.c	modified	+1	−2	View file
arch/arm/mach-kirkwood/pcie.c	modified	+6	−10	View file
arch/arm/mach-ks8695/pci.c	modified	+1	−8	View file
arch/arm/mach-mv78xx0/pcie.c	modified	+7	−17	View file
arch/arm/mach-mxs/devices-mx23.h	modified	+9	−3	View file
arch/arm/mach-mxs/devices-mx28.h	modified	+9	−3	View file
arch/arm/mach-mxs/devices.c	modified	+0	−16	View file
arch/arm/mach-mxs/devices/Makefile	modified	+0	−1	View file
arch/arm/mach-mxs/devices/amba-duart.c	deleted	+0	−40	View before deletion
arch/arm/mach-mxs/include/mach/devices-common.h	modified	+0	−5	View file
arch/arm/mach-orion5x/db88f5281-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/dns323-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/kurobox_pro-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/mss2-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/rd88f5182-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/terastation_pro2-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/ts209-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/ts409-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/wnr854t-setup.c	modified	+0	−1	View file
arch/arm/mach-orion5x/wrt350n-v2-setup.c	modified	+0	−1	View file
arch/arm/mach-pxa/cm-x2xx-pci.c	modified	+1	−2	View file
arch/arm/mach-sa1100/pci-nanoengine.c	modified	+1	−7	View file
arch/arm/mach-shark/pci.c	modified	+1	−2	View file
arch/arm/mach-tegra/pcie.c	modified	+0	−1	View file
arch/arm/mach-tegra/timer.c	modified	+3	−2	View file
arch/arm/mach-ux500/devices-common.c	modified	+0	−33	View file
arch/arm/mach-ux500/devices-common.h	modified	+10	−13	View file
arch/arm/mach-ux500/devices-db8500.h	modified	+1	−1	View file
arch/arm/mach-versatile/core.c	modified	+8	−10	View file
arch/arm/mach-versatile/pci.c	modified	+2	−11	View file
arch/arm/mach-vexpress/v2m.c	modified	+7	−1	View file
arch/arm/mm/Kconfig	modified	+1	−45	View file
arch/arm/mm/Makefile	modified	+0	−4	View file
arch/arm/mm/cache-v3.S	modified	+1	−0	View file
arch/arm/mm/cache-v4.S	modified	+1	−0	View file
arch/arm/mm/cache-v4wb.S	modified	+3	−3	View file
arch/arm/mm/cache-v4wt.S	modified	+1	−0	View file
arch/arm/mm/cache-v6.S	modified	+4	−6	View file
arch/arm/mm/cache-v7.S	modified	+4	−6	View file
arch/arm/mm/context.c	modified	+28	−29	View file
arch/arm/mm/copypage-v3.c	deleted	+0	−81	View before deletion
arch/arm/mm/fault.c	modified	+0	−3	View file
arch/arm/mm/proc-arm1020.S	modified	+1	−0	View file
arch/arm/mm/proc-arm1020e.S	modified	+1	−0	View file
arch/arm/mm/proc-arm1022.S	modified	+1	−0	View file
arch/arm/mm/proc-arm1026.S	modified	+1	−0	View file
arch/arm/mm/proc-arm6_7.S	deleted	+0	−327	View before deletion
arch/arm/mm/proc-arm920.S	modified	+1	−0	View file
arch/arm/mm/proc-arm922.S	modified	+1	−0	View file
arch/arm/mm/proc-arm925.S	modified	+1	−0	View file
arch/arm/mm/proc-arm926.S	modified	+1	−0	View file
arch/arm/mm/proc-arm940.S	modified	+3	−3	View file
arch/arm/mm/proc-arm946.S	modified	+1	−0	View file
arch/arm/mm/proc-feroceon.S	modified	+1	−0	View file
arch/arm/mm/proc-mohawk.S	modified	+1	−0	View file
arch/arm/mm/proc-v7-2level.S	modified	+2	−7	View file
arch/arm/mm/tlb-v3.S	deleted	+0	−48	View before deletion
arch/arm/plat-iop/pci.c	modified	+1	−7	View file
arch/arm/plat-omap/counter_32k.c	modified	+4	−2	View file
arch/arm/plat-versatile/Kconfig	modified	+6	−0	View file
arch/arm/plat-versatile/fpga-irq.c	modified	+101	−15	View file
arch/arm/plat-versatile/include/plat/fpga-irq.h	modified	+5	−6	View file
arch/arm/tools/mach-types	modified	+271	−234	View file
arch/arm/vfp/vfpmodule.c	modified	+8	−8	View file
drivers/amba/bus.c	modified	+51	−2	View file
drivers/mmc/host/mmci.c	modified	+17	−1	View file
include/linux/amba/bus.h	modified	+8	−0	View file

Only the first 600 diff lines are shown. Download the complete patch.

Documentation/devicetree/bindings/arm/arch_timer.txt

View file

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
new file mode 100644
index 0000000..52478c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -0,0 +1,27 @@
+* ARM architected timer
+
+ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
+provides per-cpu timers.
+
+The timer is attached to a GIC to deliver its per-processor interrupts.
+
+** Timer node properties:
+
+- compatible : Should at least contain "arm,armv7-timer".
+
+- interrupts : Interrupt list for secure, non-secure, virtual and
+  hypervisor timers, in that order.
+
+- clock-frequency : The frequency of the main counter, in Hz. Optional.
+
+Example:
+
+	timer {
+		compatible = "arm,cortex-a15-timer",
+			     "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>,
+			     <1 10 0xf08>;
+		clock-frequency = <100000000>;
+	};

arch/arm/Kconfig

View file

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e19ed3f..554ec1d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -11,6 +11,7 @@ config ARM
 	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
 	select HAVE_ARCH_KGDB
+	select HAVE_ARCH_TRACEHOOK
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@ -30,6 +31,8 @@ config ARM
 	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_GENERIC_HARDIRQS
+	select HARDIRQS_SW_RESEND
+	select GENERIC_IRQ_PROBE
 	select GENERIC_IRQ_SHOW
 	select CPU_PM if (SUSPEND || CPU_IDLE)
 	select GENERIC_PCI_IOMAP
@@ -126,14 +129,6 @@ config TRACE_IRQFLAGS_SUPPORT
 	bool
 	default y
 
-config HARDIRQS_SW_RESEND
-	bool
-	default y
-
-config GENERIC_IRQ_PROBE
-	bool
-	default y
-
 config GENERIC_LOCKBREAK
 	bool
 	default y
@@ -280,6 +275,7 @@ config ARCH_INTEGRATOR
 	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	select SPARSE_IRQ
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for ARM's Integrator platform.
 
@@ -632,7 +628,6 @@ config ARCH_MMP
 	select CLKDEV_LOOKUP
 	select GENERIC_CLOCKEVENTS
 	select GPIO_PXA
-	select TICK_ONESHOT
 	select PLAT_PXA
 	select SPARSE_IRQ
 	select GENERIC_ALLOCATOR
@@ -716,7 +711,6 @@ config ARCH_PXA
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select GPIO_PXA
-	select TICK_ONESHOT
 	select PLAT_PXA
 	select SPARSE_IRQ
 	select AUTO_ZRELADDR
@@ -783,7 +777,6 @@ config ARCH_SA1100
 	select CPU_FREQ
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP
-	select TICK_ONESHOT
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_IDE
 	select NEED_MACH_MEMORY_H
@@ -1552,10 +1545,15 @@ config HAVE_ARM_SCU
 	help
 	  This option enables support for the ARM system coherency unit
 
+config ARM_ARCH_TIMER
+	bool "Architected timer support"
+	depends on CPU_V7
+	help
+	  This option enables support for the ARM architected timer
+
 config HAVE_ARM_TWD
 	bool
 	depends on SMP
-	select TICK_ONESHOT
 	help
 	  This options enables support for the ARM timer and watchdog unit
 

arch/arm/Makefile

View file

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a207..aaf96bc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -70,8 +70,6 @@ arch-$(CONFIG_CPU_32v4)		:=-D__LINUX_ARM_ARCH__=4 -march=armv4
 arch-$(CONFIG_CPU_32v3)		:=-D__LINUX_ARM_ARCH__=3 -march=armv3
 
 # This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM610)	:=-mtune=arm610
-tune-$(CONFIG_CPU_ARM710)	:=-mtune=arm710
 tune-$(CONFIG_CPU_ARM7TDMI)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM720T)	:=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM740T)	:=-mtune=arm7tdmi

arch/arm/boot/compressed/head.S

View file

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index dc7e8ce..b8c64b8 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -567,6 +567,12 @@ __armv3_mpu_cache_on:
 		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
 		mov	pc, lr
 
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define CB_BITS 0x08
+#else
+#define CB_BITS 0x0c
+#endif
+
 __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
 		bic	r3, r3, #0xff		@ Align the pointer
 		bic	r3, r3, #0x3f00
@@ -578,17 +584,14 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
 		mov	r9, r0, lsr #18
 		mov	r9, r9, lsl #18		@ start of RAM
 		add	r10, r9, #0x10000000	@ a reasonable RAM size
-		mov	r1, #0x12
-		orr	r1, r1, #3 << 10
+		mov	r1, #0x12		@ XN|U + section mapping
+		orr	r1, r1, #3 << 10	@ AP=11
 		add	r2, r3, #16384
 1:		cmp	r1, r9			@ if virt > start of RAM
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-		orrhs	r1, r1, #0x08		@ set cacheable
-#else
-		orrhs	r1, r1, #0x0c		@ set cacheable, bufferable
-#endif
-		cmp	r1, r10			@ if virt > end of RAM
-		bichs	r1, r1, #0x0c		@ clear cacheable, bufferable
+		cmphs	r10, r1			@   && end of RAM > virt
+		bic	r1, r1, #0x1c		@ clear XN|U + C + B
+		orrlo	r1, r1, #0x10		@ Set XN|U for non-RAM
+		orrhs	r1, r1, r6		@ set RAM section settings
 		str	r1, [r0], #4		@ 1:1 mapping
 		add	r1, r1, #1048576
 		teq	r0, r2
@@ -599,7 +602,7 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
  * so there is no map overlap problem for up to 1 MB compressed kernel.
  * If the execution is in RAM then we would only be duplicating the above.
  */
-		mov	r1, #0x1e
+		orr	r1, r6, #0x04		@ ensure B is set for this
 		orr	r1, r1, #3 << 10
 		mov	r2, pc
 		mov	r2, r2, lsr #20
@@ -620,6 +623,7 @@ __arm926ejs_mmu_cache_on:
 __armv4_mmu_cache_on:
 		mov	r12, lr
 #ifdef CONFIG_MMU
+		mov	r6, #CB_BITS | 0x12	@ U
 		bl	__setup_mmu
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
@@ -641,6 +645,7 @@ __armv7_mmu_cache_on:
 #ifdef CONFIG_MMU
 		mrc	p15, 0, r11, c0, c1, 4	@ read ID_MMFR0
 		tst	r11, #0xf		@ VMSA
+		movne	r6, #CB_BITS | 0x02	@ !XN
 		blne	__setup_mmu
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
@@ -655,7 +660,7 @@ __armv7_mmu_cache_on:
 		orr	r0, r0, #1 << 25	@ big-endian page tables
 #endif
 		orrne	r0, r0, #1		@ MMU enabled
-		movne	r1, #-1
+		movne	r1, #0xfffffffd		@ domain 0 = client
 		mcrne	p15, 0, r3, c2, c0, 0	@ load page table pointer
 		mcrne	p15, 0, r1, c3, c0, 0	@ load domain access control
 #endif
@@ -668,6 +673,7 @@ __armv7_mmu_cache_on:
 
 __fa526_cache_on:
 		mov	r12, lr
+		mov	r6, #CB_BITS | 0x12	@ U
 		bl	__setup_mmu
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c7, 0	@ Invalidate whole cache
@@ -680,18 +686,6 @@ __fa526_cache_on:
 		mcr	p15, 0, r0, c8, c7, 0	@ flush UTLB
 		mov	pc, r12
 
-__arm6_mmu_cache_on:
-		mov	r12, lr
-		bl	__setup_mmu
-		mov	r0, #0
-		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
-		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3
-		mov	r0, #0x30
-		bl	__common_mmu_cache_on
-		mov	r0, #0
-		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3
-		mov	pc, r12
-
 __common_mmu_cache_on:
 #ifndef CONFIG_THUMB2_KERNEL
 #ifndef DEBUG
@@ -756,16 +750,6 @@ call_cache_fn:	adr	r12, proc_types
 		.align	2
 		.type	proc_types,#object
 proc_types:
-		.word	0x41560600		@ ARM6/610
-		.word	0xffffffe0
-		W(b)	__arm6_mmu_cache_off	@ works, but slow
-		W(b)	__arm6_mmu_cache_off
-		mov	pc, lr
- THUMB(		nop				)
-@		b	__arm6_mmu_cache_on		@ untested
-@		b	__arm6_mmu_cache_off
-@		b	__armv3_mmu_cache_flush
-
 		.word	0x00000000		@ old ARM ID
 		.word	0x0000f000
 		mov	pc, lr
@@ -777,8 +761,10 @@ proc_types:
 
 		.word	0x41007000		@ ARM7/710
 		.word	0xfff8fe00
-		W(b)	__arm7_mmu_cache_off
-		W(b)	__arm7_mmu_cache_off
+		mov	pc, lr
+ THUMB(		nop				)
+		mov	pc, lr
+ THUMB(		nop				)
 		mov	pc, lr
  THUMB(		nop				)
 
@@ -977,21 +963,6 @@ __armv7_mmu_cache_off:
 		mcr	p15, 0, r0, c7, c5, 4	@ ISB
 		mov	pc, r12
 
-__arm6_mmu_cache_off:
-		mov	r0, #0x00000030		@ ARM6 control reg.
-		b	__armv3_mmu_cache_off
-
-__arm7_mmu_cache_off:
-		mov	r0, #0x00000070		@ ARM7 control reg.
-		b	__armv3_mmu_cache_off
-
-__armv3_mmu_cache_off:
-		mcr	p15, 0, r0, c1, c0, 0	@ turn MMU and cache off
-		mov	r0, #0
-		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
-		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3
-		mov	pc, lr
-
 /*
  * Clean and flush the cache to maintain consistency.
  *

arch/arm/common/it8152.c

View file

diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index dcb1349..c4110d1 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -222,7 +222,7 @@ static int it8152_pci_write_config(struct pci_bus *bus,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static struct pci_ops it8152_ops = {
+struct pci_ops it8152_ops = {
 	.read = it8152_pci_read_config,
 	.write = it8152_pci_write_config,
 };
@@ -346,9 +346,4 @@ void pcibios_set_master(struct pci_dev *dev)
 }
 
 
-struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
-	return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);
-}
-
 EXPORT_SYMBOL(dma_set_coherent_mask);

arch/arm/common/via82c505.c

View file

diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 1171a50..6cb362e 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -51,7 +51,7 @@ via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static struct pci_ops via82c505_ops = {
+struct pci_ops via82c505_ops = {
 	.read	= via82c505_read_config,
 	.write	= via82c505_write_config,
 };
@@ -81,12 +81,3 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys)
 {
 	return (nr == 0);
 }
-
-struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
-{
-	if (nr == 0)
-		return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata,
-					 &sysdata->resources);
-
-	return NULL;
-}

arch/arm/common/vic.c

View file

diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 7e288f9..e0d5388 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -39,6 +39,7 @@
  * struct vic_device - VIC PM device
  * @irq: The IRQ number for the base of the VIC.
  * @base: The register base for the VIC.
+ * @valid_sources: A bitmask of valid interrupts
  * @resume_sources: A bitmask of interrupts for resume.
  * @resume_irqs: The IRQs enabled for resume.
  * @int_select: Save for VIC_INT_SELECT.
@@ -50,6 +51,7 @@
 struct vic_device {
 	void __iomem	*base;
 	int		irq;
+	u32		valid_sources;
 	u32		resume_sources;
 	u32		resume_irqs;
 	u32		int_select;
@@ -164,10 +166,32 @@ static int __init vic_pm_init(void)
 late_initcall(vic_pm_init);
 #endif /* CONFIG_PM */
 
+static struct irq_chip vic_chip;
+
+static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
+			     irq_hw_number_t hwirq)
+{
+	struct vic_device *v = d->host_data;
+
+	/* Skip invalid IRQs, only register handlers for the real ones */
+	if (!(v->valid_sources & (1 << hwirq)))
+		return -ENOTSUPP;
+	irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
+	irq_set_chip_data(irq, v->base);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	return 0;
+}
+
+static struct irq_domain_ops vic_irqdomain_ops = {
+	.map = vic_irqdomain_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
 /**
  * vic_register() - Register a VIC.
  * @base: The base address of the VIC.
  * @irq: The base IRQ for the VIC.
+ * @valid_sources: bitmask of valid interrupts
  * @resume_sources: bitmask of interrupts allowed for resume sources.
  * @node: The device tree node associated with the VIC.
  *
@@ -178,7 +202,8 @@ late_initcall(vic_pm_init);
  * This also configures the IRQ domain for the VIC.
  */
 static void __init vic_register(void __iomem *base, unsigned int irq,
-				u32 resume_sources, struct device_node *node)
+				u32 valid_sources, u32 resume_sources,
+				struct device_node *node)
 {
 	struct vic_device *v;
 
@@ -189,11 +214,12 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
 
 	v = &vic_devices[vic_id];
 	v->base = base;
+	v->valid_sources = valid_sources;
 	v->resume_sources = resume_sources;
 	v->irq = irq;
 	vic_id++;
-	v->domain = irq_domain_add_legacy(node, 32, irq, 0,
-					  &irq_domain_simple_ops, v);
+	v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0,
+					  &vic_irqdomain_ops, v);
 }
 
 static void vic_ack_irq(struct irq_data *d)
@@ -287,23 +313,6 @@ static void __init vic_clear_interrupts(void __iomem *base)
 	}
 }
 
-static void __init vic_set_irq_sources(void __iomem *base,
-				unsigned int irq_start, u32 vic_sources)
-{
-	unsigned int i;
-
-	for (i = 0; i < 32; i++) {
-		if (vic_sources & (1 << i)) {
-			unsigned int irq = irq_start + i;
-
-			irq_set_chip_and_handler(irq, &vic_chip,
-						 handle_level_irq);
-			irq_set_chip_data(irq, base);
-			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-		}
-	}
-}
-
 /*
  * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
  * The original cell has 32 interrupts, while the modified one has 64,
@@ -338,8 +347,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
 		writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 	}
 
-	vic_set_irq_sources(base, irq_start, vic_sources);
-	vic_register(base, irq_start, 0, node);
+	vic_register(base, irq_start, vic_sources, 0, node);
 }
 
 void __init __vic_init(void __iomem *base, unsigned int irq_start,
@@ -379,9 +387,7 @@ void __init __vic_init(void __iomem *base, unsigned int irq_start,
 
 	vic_init2(base);
 
-	vic_set_irq_sources(base, irq_start, vic_sources);
-
-	vic_register(base, irq_start, resume_sources, node);
+	vic_register(base, irq_start, vic_sources, resume_sources, node);
 }
 
 /**

arch/arm/configs/rpc_defconfig

View file

diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index af278f7..00515ef 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_RPC=y
-CONFIG_CPU_ARM610=y
-CONFIG_CPU_ARM710=y
 CONFIG_CPU_SA110=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0

arch/arm/include/asm/arch_timer.h

View file

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
new file mode 100644
index 0000000..ed2e95d
--- /dev/null
+++ b/arch/arm/include/asm/arch_timer.h
@@ -0,0 +1,19 @@
+#ifndef __ASMARM_ARCH_TIMER_H
+#define __ASMARM_ARCH_TIMER_H
+
+#ifdef CONFIG_ARM_ARCH_TIMER
+int arch_timer_of_register(void);
+int arch_timer_sched_clock_init(void);
+#else
+static inline int arch_timer_of_register(void)
+{
+	return -ENXIO;
+}
+
+static inline int arch_timer_sched_clock_init(void)
+{
+	return -ENXIO;
+}
+#endif
+
+#endif

arch/arm/include/asm/cacheflush.h

View file

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index d5d8d5c..004c1bc 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -101,7 +101,7 @@ struct cpu_cache_fns {
 	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 
 	void (*coherent_kern_range)(unsigned long, unsigned long);
-	void (*coherent_user_range)(unsigned long, unsigned long);
+	int  (*coherent_user_range)(unsigned long, unsigned long);
 	void (*flush_kern_dcache_area)(void *, size_t);
 
 	void (*dma_map_area)(const void *, size_t, int);
@@ -142,7 +142,7 @@ extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
-extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
+extern int  __cpuc_coherent_user_range(unsigned long, unsigned long);
 extern void __cpuc_flush_dcache_area(void *, size_t);
 
 /*
@@ -249,7 +249,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
  * Harvard caches are synchronised for the user space address range.
  * This is used for the ARM private sys_cacheflush system call.
  */
-#define flush_cache_user_range(vma,start,end) \
+#define flush_cache_user_range(start,end) \
 	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 
 /*

arch/arm/include/asm/cmpxchg.h

View file

diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index d41d7cb..7eb18c1 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -229,66 +229,19 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
 				       (unsigned long)(n),		\
 				       sizeof(*(ptr))))
 
-#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
-
-/*
- * Note : ARMv7-M (currently unsupported by Linux) does not support
- * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
- * not be allowed to use __cmpxchg64.
- */
-static inline unsigned long long __cmpxchg64(volatile void *ptr,
-					     unsigned long long old,
-					     unsigned long long new)
-{
-	register unsigned long long oldval asm("r0");
-	register unsigned long long __old asm("r2") = old;
-	register unsigned long long __new asm("r4") = new;
-	unsigned long res;
-
-	do {
-		asm volatile(
-		"	@ __cmpxchg8\n"
-		"	ldrexd	%1, %H1, [%2]\n"
-		"	mov	%0, #0\n"
-		"	teq	%1, %3\n"
-		"	teqeq	%H1, %H3\n"
-		"	strexdeq %0, %4, %H4, [%2]\n"
-			: "=&r" (res), "=&r" (oldval)
-			: "r" (ptr), "Ir" (__old), "r" (__new)
-			: "memory", "cc");
-	} while (res);
-
-	return oldval;
-}
-
-static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
-						unsigned long long old,
-						unsigned long long new)
-{
-	unsigned long long ret;
-
-	smp_mb();
-	ret = __cmpxchg64(ptr, old, new);
-	smp_mb();
-
-	return ret;
-}
-
-#define cmpxchg64(ptr,o,n)						\
-	((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),			\
-					    (unsigned long long)(o),	\
-					    (unsigned long long)(n)))
-
-#define cmpxchg64_local(ptr,o,n)					\
-	((__typeof__(*(ptr)))__cmpxchg64((ptr),				\
-					 (unsigned long long)(o),	\
-					 (unsigned long long)(n)))
-
-#else /* min ARCH = ARMv6 */
-
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif
+#define cmpxchg64(ptr, o, n)						\
+	((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr),	\
+						atomic64_t,		\
+						counter),		\
+					      (unsigned long)(o),	\
+					      (unsigned long)(n)))