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1;;; GNU Guix --- Functional package management for GNU
2;;; Copyright © 2026 Cayetano Santos <[email protected]>
3;;;
4;;; This file is part of GNU Guix.
5;;;
6;;; GNU Guix is free software; you can redistribute it and/or modify it
7;;; under the terms of the GNU General Public License as published by
8;;; the Free Software Foundation; either version 3 of the License, or (at
9;;; your option) any later version.
10;;;
11;;; GNU Guix is distributed in the hope that it will be useful, but
12;;; WITHOUT ANY WARRANTY; without even the implied warranty of
13;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14;;; GNU General Public License for more details.
15;;;
16;;; You should have received a copy of the GNU General Public License
17;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
18
19(define-module (gnu packages hdl)
20 #:use-module ((guix licenses) #:prefix license:)
21 #:use-module (guix build-system copy)
22 #:use-module (guix gexp)
23 #:use-module (guix git-download)
24 #:use-module (guix packages)
25 #:use-module (gnu packages electronics)
26 #:use-module (gnu packages python)
27 #:use-module (gnu packages python-science)
28 #:use-module (gnu packages python-xyz))
29
30(define-public ieee-p1076
31 (package
32 (name "ieee-p1076")
33 (version "2019")
34 (source
35 (origin
36 (method git-fetch)
37 (uri (git-reference
38 (url "https://opensource.ieee.org/vasg/Packages/")
39 (commit (string-append "1076-" version))))
40 (file-name (git-file-name name version))
41 (sha256
42 (base32 "1va626i5ww2ziw3dghw0d2mq7mrj5dwcn0h019h77866yw2pq9xn"))))
43 (build-system copy-build-system)
44 (native-inputs (list python-minimal-wrapper nvc python-vunit))
45 (arguments
46 (list
47 ;; Not all 2019 features are supported by nvc compiler.
48 ;; pass 1055 of 1648
49 #:tests? #f
50 #:install-plan
51 #~'(("ieee" "share/ieee-p1076/ieee" #:include ("vhdl"))
52 ("std" "share/ieee-p1076/std" #:include ("vhdl")))))
53 (native-search-paths
54 (list (search-path-specification
55 (variable "FW_IEEE_p1076")
56 (separator #f)
57 (files (list "share/ieee-p1076")))))
58 (home-page "https://IEEE-P1076.gitlab.io")
59 (synopsis "VHDL libraries corresponding to the IEEE 1076 standard")
60 (description
61 "Open source materials intended for reference by the IEEE standard 1076,
62as approved and published by the @acronym{VHDL, Very High Speed Hardware
63Description Language} Analysis and Standardization Group.")
64 (license license:asl2.0)))
65
66(define-public json-for-vhdl
67 ;; No tagged releases.
68 (let ((commit "0dc9e317440263cd4941f157f5e5668baa858ec2")
69 (revision "0"))
70 (package
71 (name "json-for-vhdl")
72 (version (git-version "20220905" revision commit)) ;last revision
73 (source
74 (origin
75 (method git-fetch)
76 (uri (git-reference
77 (url "https://github.com/Paebbels/JSON-for-VHDL/")
78 (commit commit)))
79 (file-name (git-file-name name version))
80 (sha256
81 (base32 "1062g2c3dpsb67zhqrn1j04p7jl28g4mcxd6nhrqqfffjsvxkpw9"))))
82 (build-system copy-build-system)
83 (arguments
84 (list
85 #:install-plan
86 #~'(("src" "share/json-for-vhdl/work/src"
87 #:include ("vhdl")))
88 #:phases
89 #~(modify-phases %standard-phases
90 ;; The examples/Encodings_VUnit test requires vhdl builtins.
91 (add-after 'unpack 'fix-check
92 (lambda _
93 (substitute* "tests/VUnit/run.py"
94 (("from_argv\\(\\)")
95 "from_argv()\nvu.add_vhdl_builtins()")))))))
96 (native-search-paths
97 (list (search-path-specification
98 (variable "FW_JSON_VHDL")
99 (separator #f)
100 (files (list "share/json-for-vhdl")))))
101 (home-page "https://github.com/Paebbels/JSON-for-VHDL/")
102 (synopsis "Parse and query JSON data structures in VHDL")
103 (description
104 "The JSON-for-VHDL library provides a parser to query JSON data
105structures from external files on disk. It provides a context to be
106used in the declarative section of design units.")
107 (license license:asl2.0))))
108
109(define-public neorv32
110 (package
111 (name "neorv32")
112 (version "1.12.7")
113 (source
114 (origin
115 (method git-fetch)
116 (uri (git-reference
117 (url "https://github.com/stnolting/neorv32")
118 (commit (string-append "v" version))))
119 (file-name (git-file-name name version))
120 (sha256
121 (base32
122 "030djnf5ww4b2w6lhb9lpprq2iawf8v93rmmgfgnbr56k4blyyk6"))))
123 (outputs
124 '("out" "neorv32"))
125 (build-system copy-build-system)
126 (arguments
127 (list
128 #:tests? #f ;FIXME: nvc checksum errors inside the build env
129 #:phases
130 #~(modify-phases %standard-phases
131 (add-after 'install 'check
132 (lambda* (#:key tests? #:allow-other-keys)
133 (when tests?
134 (substitute* '("rtl/file_list_cpu.f" "rtl/file_list_soc.f")
135 (("NEORV32_RTL_PATH_PLACEHOLDER") "rtl"))
136 (for-each
137 (lambda (f)
138 (invoke
139 "sh" "-c"
140 (format #f "cat rtl/~a.f | xargs nvc --work=neorv32 -a" f)))
141 '("file_list_soc" "file_list_cpu"))
142 (for-each
143 (lambda (f)
144 (invoke "nvc" "--work=neorv32" "-a" f))
145 `("sim/sim_uart_rx.vhd"
146 ,@(find-files "sim" "x.*\\.vhd$")
147 "sim/neorv32_tb.vhd"))
148 (invoke "nvc" "--work=neorv32" "-e" "neorv32_tb")
149 (invoke "nvc" "--work=neorv32" "-r" "--stop-time=10ms"
150 "neorv32_tb")))))
151 #:install-plan
152 #~'(("rtl" "share/neorv32/work/rtl"
153 #:exclude-regexp (".*\\.f$" ".*\\.sh$"))
154 ("rtl" "share/neorv32/neorv32/rtl"
155 #:exclude-regexp (".*\\.f$" ".*\\.sh$")
156 #:output "neorv32"))))
157 (native-inputs (list nvc))
158 (native-search-paths
159 (list (search-path-specification
160 (variable "FW_NEORV32")
161 (separator #f)
162 (files (list "share/neorv32")))))
163 (home-page "https://stnolting.github.io/neorv32/")
164 (synopsis "RISC-V soft core CPU in VHDL")
165 (description
166 "Neorv32 is a small, customizable 32 bits microcontroller-like system on
167chip written in platform-independent VHDL.")
168 (properties
169 `((output-synopsis "out" "Instance this design library as work")
170 (output-synopsis "neorv32" "Instance this design library as neorv32")))
171 (license license:bsd-3)))
172
173(define-public open-logic
174 (package
175 (name "open-logic")
176 (version "4.6.0")
177 (source
178 (origin
179 (method git-fetch)
180 (uri (git-reference
181 (url "https://github.com/open-logic/open-logic/")
182 (commit version)
183 ;; Required by the en_cl_fix submodule.
184 (recursive? #t)))
185 (file-name (git-file-name name version))
186 (sha256
187 (base32
188 "138idj84w48izd59as8593n29p305kjs65cb3vgf0aps6305l7y5"))))
189 (outputs
190 '("out" "olo"))
191 (properties
192 `((output-synopsis "out" "Instance this design library as work")
193 (output-synopsis "olo" "Instance this design library as olo")))
194 (build-system copy-build-system)
195 (arguments
196 (list
197 #:phases
198 #~(modify-phases %standard-phases
199 (add-after 'install 'check
200 (lambda* (#:key tests? inputs #:allow-other-keys)
201 (when tests?
202 (setenv "HOME" "/tmp")
203 (with-directory-excursion "3rdParty/en_cl_fix/sim"
204 (invoke "python3" "run.py" "--simulator" "nvc"
205 "-p" (number->string (parallel-job-count))
206 "--simulator-path"
207 (dirname (search-input-file inputs "bin/nvc"))))
208 (with-directory-excursion "sim"
209 (substitute* "run.py"
210 ;; This is required to comply with current VUnit, see:
211 ;; https://github.com/VUnit/vunit/issues/777
212 (("compile_builtins=False, ")
213 ""))
214 (invoke "python3" "run.py" "--nvc" "-v"
215 "-p" (number->string (parallel-job-count))))))))
216 #:install-plan
217 #~'(;; Library work.
218 ("src" "share/open-logic/work/src"
219 #:include ("vhd"))
220 ("3rdParty" "share/open-logic/work/3rdParty"
221 #:include ("vhd"))
222 ;; Library olo.
223 ("src" "share/open-logic/olo/src"
224 #:include ("vhd") #:output "olo")
225 ("3rdParty" "share/open-logic/olo/3rdParty"
226 #:include ("vhd") #:output "olo"))))
227 (native-inputs
228 (list nvc
229 python-jinja2
230 python-matplotlib
231 python-minimal
232 python-scipy
233 python-vunit))
234 (native-search-paths
235 (list (search-path-specification
236 (variable "FW_OPEN_LOGIC")
237 (separator #f)
238 (files (list "share/open-logic")))))
239 (home-page "https://github.com/open-logic/open-logic/")
240 (synopsis "Open library of VHDL standard components")
241 (description "Open Logic implements commonly used design units in a
242reusable and vendor/tool-independent way. It is written following the VHDL
2432008 standard, but can also be used from System Verilog.")
244 (license (list license:lgpl2.1
245 license:expat)))) ;en_cl_fix uses Expat license