| 1 | =================
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| 2 | PA-RISC Debugging
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| 3 | =================
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| 4 |
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| 5 | okay, here are some hints for debugging the lower-level parts of
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| 6 | linux/parisc.
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| 7 |
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| 8 |
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| 9 | 1. Absolute addresses
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| 10 | =====================
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| 11 |
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| 12 | A lot of the assembly code currently runs in real mode, which means
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| 13 | absolute addresses are used instead of virtual addresses as in the
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| 14 | rest of the kernel. To translate an absolute address to a virtual
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| 15 | address you can lookup in System.map, add __PAGE_OFFSET (0x10000000
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| 16 | currently).
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| 17 |
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| 18 |
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| 19 | 2. HPMCs
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| 20 | ========
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| 21 |
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| 22 | When real-mode code tries to access non-existent memory, you'll get
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| 23 | an HPMC instead of a kernel oops. To debug an HPMC, try to find
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| 24 | the System Responder/Requestor addresses. The System Requestor
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| 25 | address should match (one of the) processor HPAs (high addresses in
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| 26 | the I/O range); the System Responder address is the address real-mode
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| 27 | code tried to access.
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| 28 |
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| 29 | Typical values for the System Responder address are addresses larger
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| 30 | than __PAGE_OFFSET (0x10000000) which mean a virtual address didn't
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| 31 | get translated to a physical address before real-mode code tried to
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| 32 | access it.
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| 33 |
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| 34 |
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| 35 | 3. Q bit fun
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| 36 | ============
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| 37 |
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| 38 | Certain, very critical code has to clear the Q bit in the PSW. What
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| 39 | happens when the Q bit is cleared is the CPU does not update the
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| 40 | registers interruption handlers read to find out where the machine
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| 41 | was interrupted - so if you get an interruption between the instruction
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| 42 | that clears the Q bit and the RFI that sets it again you don't know
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| 43 | where exactly it happened. If you're lucky the IAOQ will point to the
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| 44 | instruction that cleared the Q bit, if you're not it points anywhere
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| 45 | at all. Usually Q bit problems will show themselves in unexplainable
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| 46 | system hangs or running off the end of physical memory.
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