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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Video Decode Accelerator With Multi Hardware
8
9maintainers:
10 - Yunfei Dong <[email protected]>
11
12description: |
13 MediaTek Video Decode Accelerator is the video decoding hardware present in
14 MediaTek SoCs that supports high-resolution decoding functionalities.
15 It consists of parent and child nodes.
16
17 The decoder hardware block diagram is shown below:
18
19 +------------------------------------------------+------------------------------+
20 | | |
21 | input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer |
22 | || || | || |
23 +--------------||-----------||-------------------+-------||---------------------+
24 LAT Workqueue | Core Workqueue <parent>
25 ---------------||-----------||-------------------|-------||----------------------
26 ||<----------||---------HW index--------->|| <child>
27 \/ \/ \/
28 +-------------------------------------------------------------+
29 | enable/disable |
30 | clk power irq iommu |
31 | (lat/lat-soc/core0/core1) |
32 +-------------------------------------------------------------+
33
34 The child nodes represent the individual hardware blocks within the decoding
35 pipeline, such as LAT-SoC, LAT and Core.
36 Each child node is responsible for managing the dedicated resources of the
37 hardware, such as clocks, power domains, interrupts and IOMMUs.
38
39 The parent node is a central point of control for the child nodes.
40 It identifies the specific video decoding pipeline architecture used by the
41 SoC, manages the shared resources like workqueues and platform data, and
42 handles V4L2 API calls on behalf of the underlying hardware.
43
44 The parent utilizes two workqueues to manage the decoding process.
45 1. LAT Workqueue, for LAT-SoC and LAT decoder:
46 Its workers take input bitstream and LAT buffer, enable the hardware for
47 decoding tasks, write the result to LAT buffer, and disable the hardware
48 after the LAT decoding is done.
49 2. Core Workqueue, for Core decoder:
50 Its workers take LAT buffer and output buffer, enable the hardware for
51 decoding tasks, write the result to output buffer, and disable the hardware
52 after the Core decoding is done.
53
54 These hardware decode each frame cyclically.
55
56 The hardware might be associated with different SMI-common devices.
57 To prevent IOMMU faults during DRAM access in such cases, each hardware with
58 the unique SMI-common device must be placed under a separate parent node in
59 the device tree.
60
61 LAT-SoC refers to another hardware block that connected to additional LARB
62 (local arbiter) ports, such as RDMA and UFO.
63 It requires independent power and clock control to work with LAT decoder, and
64 it doesn't have a dedicated interrupt.
65
66 The used video decoding pipeline architecture across various Mediatek SoC:
67 MT8195: LAT-SoC + LAT + Core
68 MT8192: LAT + Core
69 MT8188: LAT + Core
70 MT8186: Core
71
72properties:
73 compatible:
74 enum:
75 - mediatek,mt8192-vcodec-dec
76 - mediatek,mt8186-vcodec-dec
77 - mediatek,mt8188-vcodec-dec
78 - mediatek,mt8195-vcodec-dec
79
80 reg:
81 minItems: 1
82 items:
83 - description: VDEC_SYS register space
84 - description: VDEC_RACING_CTRL register space
85
86 iommus:
87 minItems: 1
88 maxItems: 32
89 description: |
90 List of the hardware port in respective IOMMU block for current Socs.
91 Refer to bindings/iommu/mediatek,iommu.yaml.
92
93 mediatek,scp:
94 $ref: /schemas/types.yaml#/definitions/phandle
95 description: |
96 The node of system control processor (SCP), using
97 the remoteproc & rpmsg framework.
98
99 "#address-cells":
100 const: 2
101
102 "#size-cells":
103 const: 2
104
105 ranges: true
106
107# Required child node:
108patternProperties:
109 '^video-codec@[0-9a-f]+$':
110 type: object
111
112 properties:
113 compatible:
114 enum:
115 - mediatek,mtk-vcodec-core
116 - mediatek,mtk-vcodec-lat
117 - mediatek,mtk-vcodec-lat-soc
118
119 reg:
120 maxItems: 1
121 description: VDEC_MISC register space
122
123 interrupts:
124 maxItems: 1
125
126 iommus:
127 minItems: 1
128 maxItems: 32
129 description: |
130 List of the hardware port in respective IOMMU block for current Socs.
131 Refer to bindings/iommu/mediatek,iommu.yaml.
132
133 clocks:
134 minItems: 4
135 maxItems: 5
136
137 clock-names:
138 minItems: 4
139 maxItems: 5
140
141 assigned-clocks:
142 maxItems: 1
143
144 assigned-clock-parents:
145 maxItems: 1
146
147 power-domains:
148 maxItems: 1
149
150 required:
151 - compatible
152 - reg
153 - iommus
154 - clocks
155 - clock-names
156 - assigned-clocks
157 - assigned-clock-parents
158 - power-domains
159
160 additionalProperties: false
161
162required:
163 - compatible
164 - reg
165 - iommus
166 - mediatek,scp
167 - ranges
168
169if:
170 properties:
171 compatible:
172 contains:
173 enum:
174 - mediatek,mtk-vcodec-core
175 - mediatek,mtk-vcodec-lat
176
177then:
178 required:
179 - interrupts
180
181allOf:
182 - if:
183 properties:
184 compatible:
185 contains:
186 enum:
187 - mediatek,mt8192-vcodec-dec
188 then:
189 properties:
190 clock-names:
191 items:
192 - const: sel
193 - const: soc-vdec
194 - const: soc-lat
195 - const: vdec
196 - const: top
197
198 - if:
199 properties:
200 compatible:
201 contains:
202 enum:
203 - mediatek,mt8195-vcodec-dec
204 then:
205 properties:
206 clock-names:
207 items:
208 - const: sel
209 - const: vdec
210 - const: lat
211 - const: top
212
213additionalProperties: false
214
215examples:
216 - |
217 #include <dt-bindings/interrupt-controller/arm-gic.h>
218 #include <dt-bindings/memory/mt8192-larb-port.h>
219 #include <dt-bindings/interrupt-controller/irq.h>
220 #include <dt-bindings/clock/mt8192-clk.h>
221 #include <dt-bindings/power/mt8192-power.h>
222
223 bus@16000000 {
224 #address-cells = <2>;
225 #size-cells = <2>;
226 ranges = <0 0x16000000 0x16000000 0 0x40000>;
227
228 video-codec@16000000 {
229 compatible = "mediatek,mt8192-vcodec-dec";
230 mediatek,scp = <&scp>;
231 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
232 #address-cells = <2>;
233 #size-cells = <2>;
234 ranges = <0 0 0 0x16000000 0 0x40000>;
235 reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
236 video-codec@10000 {
237 compatible = "mediatek,mtk-vcodec-lat";
238 reg = <0 0x10000 0 0x800>;
239 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
240 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
241 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
242 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
243 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
244 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
245 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
246 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
247 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
248 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
249 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
250 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
251 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
252 <&topckgen CLK_TOP_MAINPLL_D4>;
253 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
254 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
255 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
256 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
257 };
258
259 video-codec@25000 {
260 compatible = "mediatek,mtk-vcodec-core";
261 reg = <0 0x25000 0 0x1000>;
262 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
263 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
264 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
265 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
266 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
267 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
268 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
269 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
270 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
271 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
272 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
273 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
274 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
275 <&vdecsys CLK_VDEC_VDEC>,
276 <&vdecsys CLK_VDEC_LAT>,
277 <&vdecsys CLK_VDEC_LARB1>,
278 <&topckgen CLK_TOP_MAINPLL_D4>;
279 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
280 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
281 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
282 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
283 };
284 };
285 };