| 1 | =====================================
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| 2 | Linux I2C slave interface description
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| 3 | =====================================
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| 4 |
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| 5 | by Wolfram Sang <[email protected]> in 2014-15
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| 6 |
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| 7 | Linux can also be an I2C slave if the I2C controller in use has slave
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| 8 | functionality. For that to work, one needs slave support in the bus driver plus
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| 9 | a hardware independent software backend providing the actual functionality. An
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| 10 | example for the latter is the slave-eeprom driver, which acts as a dual memory
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| 11 | driver. While another I2C master on the bus can access it like a regular
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| 12 | EEPROM, the Linux I2C slave can access the content via sysfs and handle data as
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| 13 | needed. The backend driver and the I2C bus driver communicate via events. Here
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| 14 | is a small graph visualizing the data flow and the means by which data is
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| 15 | transported. The dotted line marks only one example. The backend could also
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| 16 | use a character device, be in-kernel only, or something completely different::
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| 17 |
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| 18 |
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| 19 | e.g. sysfs I2C slave events I/O registers
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| 20 | +-----------+ v +---------+ v +--------+ v +------------+
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| 21 | | Userspace +........+ Backend +-----------+ Driver +-----+ Controller |
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| 22 | +-----------+ +---------+ +--------+ +------------+
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| 23 | | |
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| 24 | ----------------------------------------------------------------+-- I2C
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| 25 | --------------------------------------------------------------+---- Bus
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| 26 |
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| 27 | Note: Technically, there is also the I2C core between the backend and the
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| 28 | driver. However, at this time of writing, the layer is transparent.
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| 29 |
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| 30 |
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| 31 | User manual
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| 32 | ===========
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| 33 |
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| 34 | I2C slave backends behave like standard I2C clients. So, you can instantiate
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| 35 | them as described in the document instantiating-devices.rst. The only
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| 36 | difference is that i2c slave backends have their own address space. So, you
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| 37 | have to add 0x1000 to the address you would originally request. An example for
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| 38 | instantiating the slave-eeprom driver from userspace at the 7 bit address 0x64
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| 39 | on bus 1::
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| 40 |
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| 41 | # echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-1/new_device
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| 42 |
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| 43 | Each backend should come with separate documentation to describe its specific
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| 44 | behaviour and setup.
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| 45 |
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| 46 |
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| 47 | Developer manual
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| 48 | ================
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| 49 |
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| 50 | First, the events which are used by the bus driver and the backend will be
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| 51 | described in detail. After that, some implementation hints for extending bus
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| 52 | drivers and writing backends will be given.
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| 53 |
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| 54 |
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| 55 | I2C slave events
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| 56 | ----------------
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| 57 |
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| 58 | The bus driver sends an event to the backend using the following function::
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| 59 |
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| 60 | ret = i2c_slave_event(client, event, &val)
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| 61 |
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| 62 | 'client' describes the I2C slave device. 'event' is one of the special event
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| 63 | types described hereafter. 'val' holds an u8 value for the data byte to be
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| 64 | read/written and is thus bidirectional. The pointer to val must always be
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| 65 | provided even if val is not used for an event, i.e. don't use NULL here. 'ret'
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| 66 | is the return value from the backend. Mandatory events must be provided by the
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| 67 | bus drivers and must be checked for by backend drivers.
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| 68 |
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| 69 | Event types:
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| 70 |
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| 71 | * I2C_SLAVE_WRITE_REQUESTED (mandatory)
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| 72 |
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| 73 | 'val': unused
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| 74 |
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| 75 | 'ret': 0 if the backend is ready, otherwise some errno
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| 76 |
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| 77 | Another I2C master wants to write data to us. This event should be sent once
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| 78 | our own address and the write bit was detected. The data did not arrive yet, so
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| 79 | there is nothing to process or return. After returning, the bus driver must
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| 80 | always ack the address phase. If 'ret' is zero, backend initialization or
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| 81 | wakeup is done and further data may be received. If 'ret' is an errno, the bus
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| 82 | driver should nack all incoming bytes until the next stop condition to enforce
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| 83 | a retry of the transmission.
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| 84 |
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| 85 | * I2C_SLAVE_READ_REQUESTED (mandatory)
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| 86 |
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| 87 | 'val': backend returns first byte to be sent
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| 88 |
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| 89 | 'ret': always 0
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| 90 |
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| 91 | Another I2C master wants to read data from us. This event should be sent once
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| 92 | our own address and the read bit was detected. After returning, the bus driver
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| 93 | should transmit the first byte.
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| 94 |
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| 95 | * I2C_SLAVE_WRITE_RECEIVED (mandatory)
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| 96 |
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| 97 | 'val': bus driver delivers received byte
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| 98 |
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| 99 | 'ret': 0 if the byte should be acked, some errno if the byte should be nacked
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| 100 |
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| 101 | Another I2C master has sent a byte to us which needs to be set in 'val'. If 'ret'
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| 102 | is zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte
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| 103 | should be nacked.
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| 104 |
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| 105 | * I2C_SLAVE_READ_PROCESSED (mandatory)
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| 106 |
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| 107 | 'val': backend returns next byte to be sent
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| 108 |
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| 109 | 'ret': always 0
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| 110 |
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| 111 | The bus driver requests the next byte to be sent to another I2C master in
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| 112 | 'val'. Important: This does not mean that the previous byte has been acked, it
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| 113 | only means that the previous byte is shifted out to the bus! To ensure seamless
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| 114 | transmission, most hardware requests the next byte when the previous one is
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| 115 | still shifted out. If the master sends NACK and stops reading after the byte
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| 116 | currently shifted out, this byte requested here is never used. It very likely
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| 117 | needs to be sent again on the next I2C_SLAVE_READ_REQUEST, depending a bit on
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| 118 | your backend, though.
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| 119 |
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| 120 | * I2C_SLAVE_STOP (mandatory)
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| 121 |
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| 122 | 'val': unused
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| 123 |
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| 124 | 'ret': always 0
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| 125 |
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| 126 | A stop condition was received. This can happen anytime and the backend should
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| 127 | reset its state machine for I2C transfers to be able to receive new requests.
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| 128 |
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| 129 |
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| 130 | Software backends
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| 131 | -----------------
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| 132 |
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| 133 | If you want to write a software backend:
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| 134 |
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| 135 | * use a standard i2c_driver and its matching mechanisms
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| 136 | * write the slave_callback which handles the above slave events
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| 137 | (best using a state machine)
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| 138 | * register this callback via i2c_slave_register()
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| 139 |
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| 140 | Check the i2c-slave-eeprom driver as an example.
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| 141 |
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| 142 |
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| 143 | Bus driver support
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| 144 | ------------------
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| 145 |
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| 146 | If you want to add slave support to the bus driver:
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| 147 |
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| 148 | * implement calls to register/unregister the slave and add those to the
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| 149 | struct i2c_algorithm. When registering, you probably need to set the I2C
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| 150 | slave address and enable slave specific interrupts. If you use runtime pm, you
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| 151 | should use pm_runtime_get_sync() because your device usually needs to be
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| 152 | powered on always to be able to detect its slave address. When unregistering,
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| 153 | do the inverse of the above.
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| 154 |
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| 155 | * Catch the slave interrupts and send appropriate i2c_slave_events to the backend.
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| 156 |
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| 157 | Note that most hardware supports being master _and_ slave on the same bus. So,
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| 158 | if you extend a bus driver, please make sure that the driver supports that as
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| 159 | well. In almost all cases, slave support does not need to disable the master
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| 160 | functionality.
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| 161 |
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| 162 | Check the i2c-rcar driver as an example.
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| 163 |
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| 164 |
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| 165 | About ACK/NACK
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| 166 | --------------
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| 167 |
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| 168 | It is good behaviour to always ACK the address phase, so the master knows if a
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| 169 | device is basically present or if it mysteriously disappeared. Using NACK to
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| 170 | state being busy is troublesome. SMBus demands to always ACK the address phase,
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| 171 | while the I2C specification is more loose on that. Most I2C controllers also
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| 172 | automatically ACK when detecting their slave addresses, so there is no option
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| 173 | to NACK them. For those reasons, this API does not support NACK in the address
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| 174 | phase.
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| 175 |
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| 176 | Currently, there is no slave event to report if the master did ACK or NACK a
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| 177 | byte when it reads from us. We could make this an optional event if the need
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| 178 | arises. However, cases should be extremely rare because the master is expected
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| 179 | to send STOP after that and we have an event for that. Also, keep in mind not
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| 180 | all I2C controllers have the possibility to report that event.
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| 181 |
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| 182 |
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| 183 | About buffers
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| 184 | -------------
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| 185 |
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| 186 | During development of this API, the question of using buffers instead of just
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| 187 | bytes came up. Such an extension might be possible, usefulness is unclear at
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| 188 | this time of writing. Some points to keep in mind when using buffers:
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| 189 |
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| 190 | * Buffers should be opt-in and backend drivers will always have to support
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| 191 | byte-based transactions as the ultimate fallback anyhow because this is how
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| 192 | the majority of HW works.
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| 193 |
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| 194 | * For backends simulating hardware registers, buffers are largely not helpful
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| 195 | because after each byte written an action should be immediately triggered.
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| 196 | For reads, the data kept in the buffer might get stale if the backend just
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| 197 | updated a register because of internal processing.
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| 198 |
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| 199 | * A master can send STOP at any time. For partially transferred buffers, this
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| 200 | means additional code to handle this exception. Such code tends to be
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| 201 | error-prone.
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