| 1 |
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| 2 | #ifndef _ASM_EXTABLE_H
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| 3 | #define _ASM_EXTABLE_H
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| 4 |
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| 5 | |
| 6 | * About the exception table:
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| 7 | *
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| 8 | * - insn is a 32-bit pc-relative offset from the faulting insn.
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| 9 | * - nextinsn is a 16-bit offset off of the faulting instruction
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| 10 | * (not off of the *next* instruction as branches are).
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| 11 | * - errreg is the register in which to place -EFAULT.
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| 12 | * - valreg is the final target register for the load sequence
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| 13 | * and will be zeroed.
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| 14 | *
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| 15 | * Either errreg or valreg may be $31, in which case nothing happens.
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| 16 | *
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| 17 | * The exception fixup information "just so happens" to be arranged
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| 18 | * as in a MEM format instruction. This lets us emit our three
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| 19 | * values like so:
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| 20 | *
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| 21 | * lda valreg, nextinsn(errreg)
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| 22 | *
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| 23 |
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| 24 |
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| 25 | struct exception_table_entry
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| 26 | {
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| 27 | signed int insn;
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| 28 | union exception_fixup {
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| 29 | unsigned unit;
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| 30 | struct {
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| 31 | signed int nextinsn : 16;
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| 32 | unsigned int errreg : 5;
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| 33 | unsigned int valreg : 5;
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| 34 | } bits;
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| 35 | } fixup;
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| 36 | };
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| 37 |
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| 38 |
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| 39 | #define fixup_exception(map_reg, _fixup, pc) \
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| 40 | ({ \
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| 41 | if ((_fixup)->fixup.bits.valreg != 31) \
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| 42 | map_reg((_fixup)->fixup.bits.valreg) = 0; \
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| 43 | if ((_fixup)->fixup.bits.errreg != 31) \
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| 44 | map_reg((_fixup)->fixup.bits.errreg) = -EFAULT; \
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| 45 | (pc) + (_fixup)->fixup.bits.nextinsn; \
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| 46 | })
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| 47 |
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| 48 | #define ARCH_HAS_RELATIVE_EXTABLE
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| 49 |
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| 50 | #define swap_ex_entry_fixup(a, b, tmp, delta) \
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| 51 | do { \
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| 52 | (a)->fixup.unit = (b)->fixup.unit; \
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| 53 | (b)->fixup.unit = (tmp).fixup.unit; \
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| 54 | } while (0)
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| 55 |
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| 56 | #endif
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