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| 2 | |
| 3 | * Copyright (C) 2019 Google LLC.
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| 4 |
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| 5 | #ifndef __ASM_RWONCE_H
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| 6 | #define __ASM_RWONCE_H
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| 7 |
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| 8 | #ifdef CONFIG_SMP
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| 9 |
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| 10 | #include <asm/barrier.h>
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| 11 |
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| 12 | |
| 13 | * Alpha is apparently daft enough to reorder address-dependent loads
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| 14 | * on some CPU implementations. Knock some common sense into it with
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| 15 | * a memory barrier in READ_ONCE().
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| 16 | *
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| 17 | * For the curious, more information about this unusual reordering is
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| 18 | * available in chapter 15 of the "perfbook":
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| 19 | *
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| 20 | * https://kernel.org/pub/linux/kernel/people/paulmck/perfbook/perfbook.html
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| 21 | *
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| 22 |
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| 23 | #define __READ_ONCE(x) \
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| 24 | ({ \
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| 25 | __unqual_scalar_typeof(x) __x = \
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| 26 | (*(volatile typeof(__x) *)(&(x))); \
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| 27 | mb(); \
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| 28 | (typeof(x))__x; \
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| 29 | })
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| 30 |
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| 31 | #endif
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| 32 |
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| 33 | #include <asm-generic/rwonce.h>
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| 34 |
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| 35 | #endif
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