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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/alpha/kernel/pci.c
4 *
5 * Extruded from code written by
6 * Dave Rusling ([email protected])
7 * David Mosberger ([email protected])
8 */
9
10/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <[email protected]> */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <[email protected]>
14 * PCI-PCI bridges cleanup
15 */
16#include <linux/string.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20#include <linux/kernel.h>
21#include <linux/memblock.h>
22#include <linux/module.h>
23#include <linux/cache.h>
24#include <linux/slab.h>
25#include <linux/syscalls.h>
26#include <asm/machvec.h>
27
28#include "proto.h"
29#include "pci_impl.h"
30
31
32/*
33 * Some string constants used by the various core logics.
34 */
35
36const char *const pci_io_names[] = {
37 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
38 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
39};
40
41const char *const pci_mem_names[] = {
42 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
43 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
44};
45
46const char pci_hae0_name[] = "HAE0";
47
48/*
49 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
50 * assignments.
51 */
52
53/*
54 * The PCI controller list.
55 */
56
57struct pci_controller *hose_head, **hose_tail = &hose_head;
58struct pci_controller *pci_isa_hose;
59
60/*
61 * Quirks.
62 */
63
64static void quirk_isa_bridge(struct pci_dev *dev)
65{
66 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
67}
68DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
69
70static void quirk_cypress(struct pci_dev *dev)
71{
72 /* The Notorious Cy82C693 chip. */
73
74 /* The generic legacy mode IDE fixup in drivers/pci/probe.c
75 doesn't work correctly with the Cypress IDE controller as
76 it has non-standard register layout. Fix that. */
77 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
78 dev->resource[2].start = dev->resource[3].start = 0;
79 dev->resource[2].end = dev->resource[3].end = 0;
80 dev->resource[2].flags = dev->resource[3].flags = 0;
81 if (PCI_FUNC(dev->devfn) == 2) {
82 dev->resource[0].start = 0x170;
83 dev->resource[0].end = 0x177;
84 dev->resource[1].start = 0x376;
85 dev->resource[1].end = 0x376;
86 }
87 }
88
89 /* The Cypress bridge responds on the PCI bus in the address range
90 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
91 way to turn this off. The bridge also supports several extended
92 BIOS ranges (disabled after power-up), and some consoles do turn
93 them on. So if we use a large direct-map window, or a large SG
94 window, we must avoid the entire 0xfff00000-0xffffffff region. */
95 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
96 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
97 __direct_map_size = 0xfff00000UL - __direct_map_base;
98 else {
99 struct pci_controller *hose = dev->sysdata;
100 struct pci_iommu_arena *pci = hose->sg_pci;
101 if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
102 pci->size = 0xfff00000UL - pci->dma_base;
103 }
104 }
105}
106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
107
108/* Called for each device after PCI setup is done. */
109static void pcibios_fixup_final(struct pci_dev *dev)
110{
111 unsigned int class = dev->class >> 8;
112
113 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
114 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
115 isa_bridge = dev;
116 }
117}
118DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
119
120/* Just declaring that the power-of-ten prefixes are actually the
121 power-of-two ones doesn't make it true :) */
122#define KB 1024
123#define MB (1024*KB)
124#define GB (1024*MB)
125
126resource_size_t
127pcibios_align_resource(void *data, const struct resource *res,
128 const struct resource *empty_res,
129 resource_size_t size, resource_size_t align)
130{
131 struct pci_dev *dev = data;
132 struct pci_controller *hose = dev->sysdata;
133 unsigned long alignto;
134 resource_size_t start = res->start;
135
136 if (res->flags & IORESOURCE_IO) {
137 /* Make sure we start at our min on all hoses */
138 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
139 start = PCIBIOS_MIN_IO + hose->io_space->start;
140
141 /*
142 * Put everything into 0x00-0xff region modulo 0x400
143 */
144 if (start & 0x300)
145 start = (start + 0x3ff) & ~0x3ff;
146 }
147 else if (res->flags & IORESOURCE_MEM) {
148 /* Make sure we start at our min on all hoses */
149 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
150 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
151
152 /*
153 * The following holds at least for the Low Cost
154 * Alpha implementation of the PCI interface:
155 *
156 * In sparse memory address space, the first
157 * octant (16MB) of every 128MB segment is
158 * aliased to the very first 16 MB of the
159 * address space (i.e., it aliases the ISA
160 * memory address space). Thus, we try to
161 * avoid allocating PCI devices in that range.
162 * Can be allocated in 2nd-7th octant only.
163 * Devices that need more than 112MB of
164 * address space must be accessed through
165 * dense memory space only!
166 */
167
168 /* Align to multiple of size of minimum base. */
169 alignto = max_t(resource_size_t, 0x1000, align);
170 start = ALIGN(start, alignto);
171 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
172 if (((start / (16*MB)) & 0x7) == 0) {
173 start &= ~(128*MB - 1);
174 start += 16*MB;
175 start = ALIGN(start, alignto);
176 }
177 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
178 start &= ~(128*MB - 1);
179 start += (128 + 16)*MB;
180 start = ALIGN(start, alignto);
181 }
182 }
183 }
184
185 return start;
186}
187#undef KB
188#undef MB
189#undef GB
190
191static int __init
192pcibios_init(void)
193{
194 if (alpha_mv.init_pci)
195 alpha_mv.init_pci();
196 return 0;
197}
198
199subsys_initcall(pcibios_init);
200
201#ifdef ALPHA_RESTORE_SRM_SETUP
202/* Store PCI device configuration left by SRM here. */
203struct pdev_srm_saved_conf
204{
205 struct pdev_srm_saved_conf *next;
206 struct pci_dev *dev;
207};
208
209static struct pdev_srm_saved_conf *srm_saved_configs;
210
211static void pdev_save_srm_config(struct pci_dev *dev)
212{
213 struct pdev_srm_saved_conf *tmp;
214 static int printed = 0;
215
216 if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
217 return;
218
219 if (!printed) {
220 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
221 printed = 1;
222 }
223
224 tmp = kmalloc_obj(*tmp);
225 if (!tmp) {
226 printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
227 return;
228 }
229 tmp->next = srm_saved_configs;
230 tmp->dev = dev;
231
232 pci_save_state(dev);
233
234 srm_saved_configs = tmp;
235}
236
237void
238pci_restore_srm_config(void)
239{
240 struct pdev_srm_saved_conf *tmp;
241
242 /* No need to restore if probed only. */
243 if (pci_has_flag(PCI_PROBE_ONLY))
244 return;
245
246 /* Restore SRM config. */
247 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
248 pci_restore_state(tmp->dev);
249 }
250}
251#else
252#define pdev_save_srm_config(dev) do {} while (0)
253#endif
254
255void pcibios_fixup_bus(struct pci_bus *bus)
256{
257 struct pci_dev *dev = bus->self;
258
259 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
260 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
261 pci_read_bridge_bases(bus);
262 }
263
264 list_for_each_entry(dev, &bus->devices, bus_list) {
265 pdev_save_srm_config(dev);
266 }
267}
268
269/*
270 * If we set up a device for bus mastering, we need to check the latency
271 * timer as certain firmware forgets to set it properly, as seen
272 * on SX164 and LX164 with SRM.
273 */
274void
275pcibios_set_master(struct pci_dev *dev)
276{
277 u8 lat;
278 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
279 if (lat >= 16) return;
280 printk("PCI: Setting latency timer of device %s to 64\n",
281 pci_name(dev));
282 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
283}
284
285void __init
286pcibios_claim_one_bus(struct pci_bus *b)
287{
288 struct pci_dev *dev;
289 struct pci_bus *child_bus;
290
291 list_for_each_entry(dev, &b->devices, bus_list) {
292 struct resource *r;
293 int i;
294
295 pci_dev_for_each_resource(dev, r, i) {
296 if (r->parent || !r->start || !r->flags)
297 continue;
298 if (pci_has_flag(PCI_PROBE_ONLY) ||
299 (r->flags & IORESOURCE_PCI_FIXED)) {
300 if (pci_claim_resource(dev, i) == 0)
301 continue;
302
303 pci_claim_bridge_resource(dev, i);
304 }
305 }
306 }
307
308 list_for_each_entry(child_bus, &b->children, node)
309 pcibios_claim_one_bus(child_bus);
310}
311
312static void __init
313pcibios_claim_console_setup(void)
314{
315 struct pci_bus *b;
316
317 list_for_each_entry(b, &pci_root_buses, node)
318 pcibios_claim_one_bus(b);
319}
320
321void __init
322common_init_pci(void)
323{
324 struct pci_controller *hose;
325 struct list_head resources;
326 struct pci_host_bridge *bridge;
327 struct pci_bus *bus;
328 int ret, next_busno;
329 int need_domain_info = 0;
330 u32 pci_mem_end;
331 u32 sg_base;
332 unsigned long end;
333
334 /* Scan all of the recorded PCI controllers. */
335 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
336 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
337
338 /* Adjust hose mem_space limit to prevent PCI allocations
339 in the iommu windows. */
340 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
341 end = hose->mem_space->start + pci_mem_end;
342 if (hose->mem_space->end > end)
343 hose->mem_space->end = end;
344
345 INIT_LIST_HEAD(&resources);
346 pci_add_resource_offset(&resources, hose->io_space,
347 hose->io_space->start);
348 pci_add_resource_offset(&resources, hose->mem_space,
349 hose->mem_space->start);
350
351 bridge = pci_alloc_host_bridge(0);
352 if (!bridge)
353 continue;
354
355 list_splice_init(&resources, &bridge->windows);
356 bridge->dev.parent = NULL;
357 bridge->sysdata = hose;
358 bridge->busnr = next_busno;
359 bridge->ops = alpha_mv.pci_ops;
360 bridge->swizzle_irq = alpha_mv.pci_swizzle;
361 bridge->map_irq = alpha_mv.pci_map_irq;
362
363 ret = pci_scan_root_bus_bridge(bridge);
364 if (ret) {
365 pci_free_host_bridge(bridge);
366 continue;
367 }
368
369 bus = hose->bus = bridge->bus;
370 hose->need_domain_info = need_domain_info;
371 next_busno = bus->busn_res.end + 1;
372 /* Don't allow 8-bit bus number overflow inside the hose -
373 reserve some space for bridges. */
374 if (next_busno > 224) {
375 next_busno = 0;
376 need_domain_info = 1;
377 }
378 }
379
380 pcibios_claim_console_setup();
381
382 pci_assign_unassigned_resources();
383 for (hose = hose_head; hose; hose = hose->next) {
384 bus = hose->bus;
385 if (bus)
386 pci_bus_add_devices(bus);
387 }
388}
389
390struct pci_controller * __init
391alloc_pci_controller(void)
392{
393 struct pci_controller *hose;
394
395 hose = memblock_alloc_or_panic(sizeof(*hose), SMP_CACHE_BYTES);
396
397 *hose_tail = hose;
398 hose_tail = &hose->next;
399
400 return hose;
401}
402
403struct resource * __init
404alloc_resource(void)
405{
406 return memblock_alloc_or_panic(sizeof(struct resource), SMP_CACHE_BYTES);
407}
408
409
410/* Provide information on locations of various I/O regions in physical
411 memory. Do this on a per-card basis so that we choose the right hose. */
412
413SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus,
414 unsigned long, dfn)
415{
416 struct pci_controller *hose;
417 struct pci_dev *dev;
418
419 /* from hose or from bus.devfn */
420 if (which & IOBASE_FROM_HOSE) {
421 for(hose = hose_head; hose; hose = hose->next)
422 if (hose->index == bus) break;
423 if (!hose) return -ENODEV;
424 } else {
425 /* Special hook for ISA access. */
426 if (bus == 0 && dfn == 0) {
427 hose = pci_isa_hose;
428 } else {
429 dev = pci_get_domain_bus_and_slot(0, bus, dfn);
430 if (!dev)
431 return -ENODEV;
432 hose = dev->sysdata;
433 pci_dev_put(dev);
434 }
435 }
436
437 switch (which & ~IOBASE_FROM_HOSE) {
438 case IOBASE_HOSE:
439 return hose->index;
440 case IOBASE_SPARSE_MEM:
441 return hose->sparse_mem_base;
442 case IOBASE_DENSE_MEM:
443 return hose->dense_mem_base;
444 case IOBASE_SPARSE_IO:
445 return hose->sparse_io_base;
446 case IOBASE_DENSE_IO:
447 return hose->dense_io_base;
448 case IOBASE_ROOT_BUS:
449 return hose->bus->number;
450 }
451
452 return -EOPNOTSUPP;
453}
454
455/* Destroy an __iomem token. Not copied from lib/iomap.c. */
456
457void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
458{
459 if (__is_mmio(addr))
460 iounmap(addr);
461}
462
463EXPORT_SYMBOL(pci_iounmap);
464
465/* FIXME: Some boxes have multiple ISA bridges! */
466struct pci_dev *isa_bridge;
467EXPORT_SYMBOL(isa_bridge);