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128 lines · 3.5 KiB

1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6#ifndef __ARC_ASM_CACHE_H
7#define __ARC_ASM_CACHE_H
8
9/* In case $$ not config, setup a dummy number for rest of kernel */
10#ifndef CONFIG_ARC_CACHE_LINE_SHIFT
11#define L1_CACHE_SHIFT 6
12#else
13#define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT
14#endif
15
16#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
17#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))
18
19/*
20 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
21 * Ideal for wiring memory mapped peripherals as we don't need to do
22 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
23 */
24#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
25
26#ifndef __ASSEMBLER__
27
28#include <linux/build_bug.h>
29
30/* Uncached access macros */
31#define arc_read_uncached_32(ptr) \
32({ \
33 unsigned int __ret; \
34 __asm__ __volatile__( \
35 " ld.di %0, [%1] \n" \
36 : "=r"(__ret) \
37 : "r"(ptr)); \
38 __ret; \
39})
40
41#define arc_write_uncached_32(ptr, data)\
42({ \
43 __asm__ __volatile__( \
44 " st.di %0, [%1] \n" \
45 : \
46 : "r"(data), "r"(ptr)); \
47})
48
49/* Largest line length for either L1 or L2 is 128 bytes */
50#define SMP_CACHE_BYTES 128
51#define cache_line_size() SMP_CACHE_BYTES
52#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES
53
54/*
55 * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
56 * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
57 * alignment for any atomic64_t embedded in buffer.
58 * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
59 * value of 4 (and not 8) in ARC ABI.
60 */
61#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
62#define ARCH_SLAB_MINALIGN 8
63#endif
64
65extern int ioc_enable;
66extern unsigned long perip_base, perip_end;
67
68#endif /* !__ASSEMBLER__ */
69
70/* Instruction cache related Auxiliary registers */
71#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
72#define ARC_REG_IC_IVIC 0x10
73#define ARC_REG_IC_CTRL 0x11
74#define ARC_REG_IC_IVIR 0x16
75#define ARC_REG_IC_ENDR 0x17
76#define ARC_REG_IC_IVIL 0x19
77#define ARC_REG_IC_PTAG 0x1E
78#define ARC_REG_IC_PTAG_HI 0x1F
79
80/* Bit val in IC_CTRL */
81#define IC_CTRL_DIS 0x1
82
83/* Data cache related Auxiliary registers */
84#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
85#define ARC_REG_DC_IVDC 0x47
86#define ARC_REG_DC_CTRL 0x48
87#define ARC_REG_DC_IVDL 0x4A
88#define ARC_REG_DC_FLSH 0x4B
89#define ARC_REG_DC_FLDL 0x4C
90#define ARC_REG_DC_STARTR 0x4D
91#define ARC_REG_DC_ENDR 0x4E
92#define ARC_REG_DC_PTAG 0x5C
93#define ARC_REG_DC_PTAG_HI 0x5F
94
95/* Bit val in DC_CTRL */
96#define DC_CTRL_DIS 0x001
97#define DC_CTRL_INV_MODE_FLUSH 0x040
98#define DC_CTRL_FLUSH_STATUS 0x100
99#define DC_CTRL_RGN_OP_INV 0x200
100#define DC_CTRL_RGN_OP_MSK 0x200
101
102/*System-level cache (L2 cache) related Auxiliary registers */
103#define ARC_REG_SLC_CFG 0x901
104#define ARC_REG_SLC_CTRL 0x903
105#define ARC_REG_SLC_FLUSH 0x904
106#define ARC_REG_SLC_INVALIDATE 0x905
107#define ARC_AUX_SLC_IVDL 0x910
108#define ARC_AUX_SLC_FLDL 0x912
109#define ARC_REG_SLC_RGN_START 0x914
110#define ARC_REG_SLC_RGN_START1 0x915
111#define ARC_REG_SLC_RGN_END 0x916
112#define ARC_REG_SLC_RGN_END1 0x917
113
114/* Bit val in SLC_CONTROL */
115#define SLC_CTRL_DIS 0x001
116#define SLC_CTRL_IM 0x040
117#define SLC_CTRL_BUSY 0x100
118#define SLC_CTRL_RGN_OP_INV 0x200
119
120/* IO coherency related Auxiliary registers */
121#define ARC_REG_IO_COH_ENABLE 0x500
122#define ARC_IO_COH_ENABLE_BIT BIT(0)
123#define ARC_REG_IO_COH_PARTIAL 0x501
124#define ARC_IO_COH_PARTIAL_BIT BIT(0)
125#define ARC_REG_IO_COH_AP0_BASE 0x508
126#define ARC_REG_IO_COH_AP0_SIZE 0x509
127
128#endif /* _ASM_CACHE_H */