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| 2 | |
| 3 | * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
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| 4 |
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| 5 |
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| 6 | #include <linux/interrupt.h>
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| 7 | #include <linux/module.h>
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| 8 | #include <linux/of.h>
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| 9 | #include <linux/irqdomain.h>
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| 10 | #include <linux/irqchip.h>
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| 11 | #include <asm/irq.h>
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| 12 |
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| 13 | #define NR_CPU_IRQS 32
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| 14 | #define TIMER0_IRQ 3
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| 15 |
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| 16 | |
| 17 | * Early Hardware specific Interrupt setup
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| 18 | * -Platform independent, needed for each CPU (not foldable into init_IRQ)
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| 19 | * -Called very early (start_kernel -> setup_arch -> setup_processor)
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| 20 | *
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| 21 | * what it does ?
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| 22 | * -Optionally, setup the High priority Interrupts as Level 2 IRQs
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| 23 |
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| 24 | void arc_init_IRQ(void)
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| 25 | {
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| 26 | unsigned int level_mask = 0, i;
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| 27 |
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| 28 |
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| 29 | level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
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| 30 |
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| 31 | |
| 32 | * Write to register, even if no LV2 IRQs configured to reset it
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| 33 | * in case bootloader had mucked with it
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| 34 |
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| 35 | write_aux_reg(AUX_IRQ_LEV, level_mask);
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| 36 |
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| 37 | if (level_mask)
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| 38 | pr_info("Level-2 interrupts bitset %x\n", level_mask);
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| 39 |
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| 40 | |
| 41 | * Disable all IRQ lines so faulty external hardware won't
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| 42 | * trigger interrupt that kernel is not ready to handle.
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| 43 |
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| 44 | for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
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| 45 | unsigned int ienb;
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| 46 |
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| 47 | ienb = read_aux_reg(AUX_IENABLE);
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| 48 | ienb &= ~(1 << i);
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| 49 | write_aux_reg(AUX_IENABLE, ienb);
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| 50 | }
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| 51 | }
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| 52 |
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| 53 | |
| 54 | * ARC700 core includes a simple on-chip intc supporting
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| 55 | * -per IRQ enable/disable
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| 56 | * -2 levels of interrupts (high/low)
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| 57 | * -all interrupts being level triggered
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| 58 | *
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| 59 | * To reduce platform code, we assume all IRQs directly hooked-up into intc.
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| 60 | * Platforms with external intc, hence cascaded IRQs, are free to over-ride
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| 61 | * below, per IRQ.
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| 62 |
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| 63 |
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| 64 | static void arc_irq_mask(struct irq_data *data)
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| 65 | {
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| 66 | unsigned int ienb;
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| 67 |
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| 68 | ienb = read_aux_reg(AUX_IENABLE);
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| 69 | ienb &= ~(1 << data->hwirq);
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| 70 | write_aux_reg(AUX_IENABLE, ienb);
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| 71 | }
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| 72 |
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| 73 | static void arc_irq_unmask(struct irq_data *data)
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| 74 | {
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| 75 | unsigned int ienb;
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| 76 |
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| 77 | ienb = read_aux_reg(AUX_IENABLE);
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| 78 | ienb |= (1 << data->hwirq);
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| 79 | write_aux_reg(AUX_IENABLE, ienb);
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| 80 | }
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| 81 |
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| 82 | static struct irq_chip onchip_intc = {
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| 83 | .name = "ARC In-core Intc",
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| 84 | .irq_mask = arc_irq_mask,
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| 85 | .irq_unmask = arc_irq_unmask,
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| 86 | };
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| 87 |
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| 88 | static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
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| 89 | irq_hw_number_t hw)
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| 90 | {
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| 91 | switch (hw) {
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| 92 | case TIMER0_IRQ:
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| 93 | irq_set_percpu_devid(irq);
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| 94 | irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
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| 95 | break;
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| 96 | default:
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| 97 | irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
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| 98 | }
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| 99 | return 0;
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| 100 | }
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| 101 |
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| 102 | static const struct irq_domain_ops arc_intc_domain_ops = {
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| 103 | .xlate = irq_domain_xlate_onecell,
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| 104 | .map = arc_intc_domain_map,
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| 105 | };
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| 106 |
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| 107 | static int __init
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| 108 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
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| 109 | {
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| 110 | struct irq_domain *root_domain;
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| 111 |
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| 112 | if (parent)
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| 113 | panic("DeviceTree incore intc not a root irq controller\n");
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| 114 |
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| 115 | root_domain = irq_domain_create_linear(of_fwnode_handle(intc),
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| 116 | NR_CPU_IRQS,
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| 117 | &arc_intc_domain_ops, NULL);
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| 118 | if (!root_domain)
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| 119 | panic("root irq domain not avail\n");
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| 120 |
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| 121 | |
| 122 | * Needed for primary domain lookup to succeed
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| 123 | * This is a primary irqchip, and can never have a parent
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| 124 |
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| 125 | irq_set_default_domain(root_domain);
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| 126 |
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| 127 | return 0;
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| 128 | }
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| 129 |
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| 130 | IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
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| 131 |
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| 132 | |
| 133 | * arch_local_irq_enable - Enable interrupts.
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| 134 | *
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| 135 | * 1. Explicitly called to re-enable interrupts
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| 136 | * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
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| 137 | * which maybe in hard ISR itself
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| 138 | *
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| 139 | * Semantics of this function change depending on where it is called from:
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| 140 | *
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| 141 | * -If called from hard-ISR, it must not invert interrupt priorities
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| 142 | * e.g. suppose TIMER is high priority (Level 2) IRQ
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| 143 | * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
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| 144 | * Here local_irq_enable( ) shd not re-enable lower priority interrupts
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| 145 | * -If called from soft-ISR, it must re-enable all interrupts
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| 146 | * soft ISR are low priority jobs which can be very slow, thus all IRQs
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| 147 | * must be enabled while they run.
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| 148 | * Now hardware context wise we may still be in L2 ISR (not done rtie)
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| 149 | * still we must re-enable both L1 and L2 IRQs
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| 150 | * Another twist is prev scenario with flow being
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| 151 | * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
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| 152 | * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
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| 153 | * over-written (this is deficiency in ARC700 Interrupt mechanism)
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| 154 |
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| 155 |
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| 156 | #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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| 157 |
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| 158 | void arch_local_irq_enable(void)
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| 159 | {
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| 160 | unsigned long flags = arch_local_save_flags();
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| 161 |
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| 162 | if (flags & STATUS_A2_MASK)
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| 163 | flags |= STATUS_E2_MASK;
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| 164 | else if (flags & STATUS_A1_MASK)
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| 165 | flags |= STATUS_E1_MASK;
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| 166 |
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| 167 | arch_local_irq_restore(flags);
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| 168 | }
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| 169 |
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| 170 | EXPORT_SYMBOL(arch_local_irq_enable);
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| 171 | #endif
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