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| 2 | |
| 3 | * arch/arm/include/asm/cache.h
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| 4 |
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| 5 | #ifndef __ASMARM_CACHE_H
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| 6 | #define __ASMARM_CACHE_H
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| 7 |
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| 8 | #define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT
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| 9 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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| 10 |
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| 11 | |
| 12 | * Memory returned by kmalloc() may be used for DMA, so we must make
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| 13 | * sure that all such allocations are cache aligned. Otherwise,
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| 14 | * unrelated code may cause parts of the buffer to be read into the
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| 15 | * cache before the transfer is done, causing old data to be seen by
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| 16 | * the CPU.
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| 17 |
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| 18 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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| 19 |
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| 20 | |
| 21 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
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| 22 |
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| 23 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
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| 24 | #define ARCH_SLAB_MINALIGN 8
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| 25 | #endif
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| 26 |
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| 27 | #define __read_mostly __section(".data..read_mostly")
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| 28 |
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| 29 | #ifndef __ASSEMBLY__
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| 30 | #ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
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| 31 | int cache_line_size(void);
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| 32 | #endif
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| 33 | #endif
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| 34 |
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| 35 | #endif
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