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| 2 | |
| 3 | * Copyright 2012 Calxeda, Inc.
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| 4 |
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| 5 | #ifndef _ASM_ARM_PERCPU_H_
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| 6 | #define _ASM_ARM_PERCPU_H_
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| 7 |
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| 8 | #include <asm/insn.h>
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| 9 |
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| 10 | register unsigned long current_stack_pointer asm ("sp");
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| 11 |
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| 12 | |
| 13 | * Same as asm-generic/percpu.h, except that we store the per cpu offset
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| 14 | * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7
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| 15 |
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| 16 | #ifdef CONFIG_SMP
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| 17 | static inline void set_my_cpu_offset(unsigned long off)
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| 18 | {
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| 19 | extern unsigned int smp_on_up;
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| 20 |
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| 21 | if (IS_ENABLED(CONFIG_CPU_V6) && !smp_on_up)
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| 22 | return;
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| 23 |
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| 24 |
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| 25 | asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory");
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| 26 | }
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| 27 |
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| 28 | static __always_inline unsigned long __my_cpu_offset(void)
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| 29 | {
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| 30 | unsigned long off;
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| 31 |
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| 32 | |
| 33 | * Read TPIDRPRW.
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| 34 | * We want to allow caching the value, so avoid using volatile and
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| 35 | * instead use a fake stack read to hazard against barrier().
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| 36 |
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| 37 | asm("0: mrc p15, 0, %0, c13, c0, 4 \n\t"
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| 38 | #ifdef CONFIG_CPU_V6
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| 39 | "1: \n\t"
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| 40 | " .subsection 1 \n\t"
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| 41 | #if defined(CONFIG_ARM_HAS_GROUP_RELOCS) && \
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| 42 | !(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
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| 43 | "2: " LOAD_SYM_ARMV6(%0, __per_cpu_offset) " \n\t"
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| 44 | " b 1b \n\t"
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| 45 | #else
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| 46 | "2: ldr %0, 3f \n\t"
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| 47 | " ldr %0, [%0] \n\t"
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| 48 | " b 1b \n\t"
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| 49 | "3: .long __per_cpu_offset \n\t"
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| 50 | #endif
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| 51 | " .previous \n\t"
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| 52 | " .pushsection \".alt.smp.init\", \"a\" \n\t"
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| 53 | " .long 0b - . \n\t"
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| 54 | " b . + (2b - 0b) \n\t"
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| 55 | " .popsection \n\t"
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| 56 | #endif
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| 57 | : "=r" (off)
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| 58 | : "Q" (*(const unsigned long *)current_stack_pointer));
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| 59 |
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| 60 | return off;
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| 61 | }
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| 62 | #define __my_cpu_offset __my_cpu_offset()
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| 63 | #else
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| 64 | #define set_my_cpu_offset(x) do {} while(0)
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| 65 |
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| 66 | #endif
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| 67 |
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| 68 | #include <asm-generic/percpu.h>
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| 69 |
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| 70 | #endif
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