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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/pgtable.h
4 *
5 * Copyright (C) 1995-2002 Russell King
6 */
7#ifndef _ASMARM_PGTABLE_H
8#define _ASMARM_PGTABLE_H
9
10#include <linux/const.h>
11#include <asm/proc-fns.h>
12
13#include <asm-generic/pgtable-nopud.h>
14
15#ifndef CONFIG_MMU
16#include <asm/pgtable-nommu.h>
17
18#else
19
20#include <asm/page.h>
21#include <asm/pgtable-hwdef.h>
22
23
24#include <asm/tlbflush.h>
25
26#ifdef CONFIG_ARM_LPAE
27#include <asm/pgtable-3level.h>
28#else
29#include <asm/pgtable-2level.h>
30#endif
31
32/*
33 * Just any arbitrary offset to the start of the vmalloc VM area: the
34 * current 8MB value just means that there will be a 8MB "hole" after the
35 * physical memory until the kernel virtual memory starts. That means that
36 * any out-of-bounds memory accesses will hopefully be caught.
37 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
38 * area for the same reason. ;)
39 */
40#define VMALLOC_OFFSET (8*1024*1024)
41#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
42#define VMALLOC_END 0xff800000UL
43
44#define LIBRARY_TEXT_START 0x0c000000
45
46#ifndef __ASSEMBLY__
47extern void __pte_error(const char *file, int line, pte_t);
48extern void __pmd_error(const char *file, int line, pmd_t);
49extern void __pgd_error(const char *file, int line, pgd_t);
50
51#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
52#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
53#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
54
55/*
56 * This is the lowest virtual address we can permit any user space
57 * mapping to be mapped at. This is particularly important for
58 * non-high vector CPUs.
59 */
60#define FIRST_USER_ADDRESS (PAGE_SIZE * 2)
61
62/*
63 * Use TASK_SIZE as the ceiling argument for free_pgtables() and
64 * free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
65 * page shared between user and kernel).
66 */
67#ifdef CONFIG_ARM_LPAE
68#define USER_PGTABLES_CEILING TASK_SIZE
69#endif
70
71/*
72 * The pgprot_* and protection_map entries will be fixed up in runtime
73 * to include the cachable and bufferable bits based on memory policy,
74 * as well as any architecture dependent bits like global/ASID and SMP
75 * shared mapping bits.
76 */
77#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG
78
79extern pgprot_t pgprot_user;
80extern pgprot_t pgprot_kernel;
81
82#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
83
84#define PAGE_NONE _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
85#define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
86#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER)
87#define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
88#define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
89#define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
90#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
91#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
92#define PAGE_KERNEL_EXEC pgprot_kernel
93
94#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
95#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
96#define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
97#define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
98#define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
99#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
100#define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
101
102#define __pgprot_modify(prot,mask,bits) \
103 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
104
105#define pgprot_noncached(prot) \
106 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
107
108#define pgprot_writecombine(prot) \
109 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
110
111#define pgprot_stronglyordered(prot) \
112 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
113
114#define pgprot_device(prot) \
115 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
116
117#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
118#define pgprot_dmacoherent(prot) \
119 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
120#define __HAVE_PHYS_MEM_ACCESS_PROT
121struct file;
122extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
123 unsigned long size, pgprot_t vma_prot);
124#else
125#define pgprot_dmacoherent(prot) \
126 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
127#endif
128
129#endif /* __ASSEMBLY__ */
130
131/*
132 * The table below defines the page protection levels that we insert into our
133 * Linux page table version. These get translated into the best that the
134 * architecture can perform. Note that on most ARM hardware:
135 * 1) We cannot do execute protection
136 * 2) If we could do execute protection, then read is implied
137 * 3) write implies read permissions
138 */
139
140#ifndef __ASSEMBLY__
141
142extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
143
144#define pgdp_get(pgpd) READ_ONCE(*pgdp)
145
146#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
147#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
148
149#define pmd_none(pmd) (!pmd_val(pmd))
150
151static inline pte_t *pmd_page_vaddr(pmd_t pmd)
152{
153 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
154}
155
156#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
157
158#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
159#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
160
161#define pte_page(pte) pfn_to_page(pte_pfn(pte))
162
163#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
164
165#define pte_isset(pte, val) ((u32)(val) == (val) ? pte_val(pte) & (val) \
166 : !!(pte_val(pte) & (val)))
167#define pte_isclear(pte, val) (!(pte_val(pte) & (val)))
168
169#define pte_none(pte) (!pte_val(pte))
170#define pte_present(pte) (pte_isset((pte), L_PTE_PRESENT))
171#define pte_valid(pte) (pte_isset((pte), L_PTE_VALID))
172#define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
173#define pte_write(pte) (pte_isclear((pte), L_PTE_RDONLY))
174#define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY))
175#define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG))
176#define pte_exec(pte) (pte_isclear((pte), L_PTE_XN))
177
178#define pte_valid_user(pte) \
179 (pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
180
181static inline bool pte_access_permitted(pte_t pte, bool write)
182{
183 pteval_t mask = L_PTE_PRESENT | L_PTE_USER;
184 pteval_t needed = mask;
185
186 if (write)
187 mask |= L_PTE_RDONLY;
188
189 return (pte_val(pte) & mask) == needed;
190}
191#define pte_access_permitted pte_access_permitted
192
193#if __LINUX_ARM_ARCH__ < 6
194static inline void __sync_icache_dcache(pte_t pteval)
195{
196}
197#else
198extern void __sync_icache_dcache(pte_t pteval);
199#endif
200
201#define PFN_PTE_SHIFT PAGE_SHIFT
202
203void set_ptes(struct mm_struct *mm, unsigned long addr,
204 pte_t *ptep, pte_t pteval, unsigned int nr);
205#define set_ptes set_ptes
206
207static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
208{
209 pte_val(pte) &= ~pgprot_val(prot);
210 return pte;
211}
212
213static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
214{
215 pte_val(pte) |= pgprot_val(prot);
216 return pte;
217}
218
219static inline pte_t pte_wrprotect(pte_t pte)
220{
221 return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
222}
223
224static inline pte_t pte_mkwrite_novma(pte_t pte)
225{
226 return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
227}
228
229static inline pte_t pte_mkclean(pte_t pte)
230{
231 return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
232}
233
234static inline pte_t pte_mkdirty(pte_t pte)
235{
236 return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
237}
238
239static inline pte_t pte_mkold(pte_t pte)
240{
241 return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
242}
243
244static inline pte_t pte_mkyoung(pte_t pte)
245{
246 return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
247}
248
249static inline pte_t pte_mkexec(pte_t pte)
250{
251 return clear_pte_bit(pte, __pgprot(L_PTE_XN));
252}
253
254static inline pte_t pte_mknexec(pte_t pte)
255{
256 return set_pte_bit(pte, __pgprot(L_PTE_XN));
257}
258
259static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
260{
261 const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
262 L_PTE_NONE | L_PTE_VALID;
263 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
264 return pte;
265}
266
267/*
268 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
269 * are !pte_none() && !pte_present().
270 *
271 * Format of swap PTEs:
272 *
273 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
274 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
275 * <------------------- offset ------------------> E < type -> 0 0
276 *
277 * E is the exclusive marker that is not stored in swap entries.
278 *
279 * This gives us up to 31 swap files and 64GB per swap file. Note that
280 * the offset field is always non-zero.
281 */
282#define __SWP_TYPE_SHIFT 2
283#define __SWP_TYPE_BITS 5
284#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
285#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
286
287#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
288#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
289#define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
290 ((offset) << __SWP_OFFSET_SHIFT) })
291
292#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
293#define __swp_entry_to_pte(swp) __pte((swp).val)
294
295static inline bool pte_swp_exclusive(pte_t pte)
296{
297 return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
298}
299
300static inline pte_t pte_swp_mkexclusive(pte_t pte)
301{
302 return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
303}
304
305static inline pte_t pte_swp_clear_exclusive(pte_t pte)
306{
307 return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
308}
309
310/*
311 * It is an error for the kernel to have more swap files than we can
312 * encode in the PTEs. This ensures that we know when MAX_SWAPFILES
313 * is increased beyond what we presently support.
314 */
315#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
316
317/*
318 * We provide our own arch_get_unmapped_area to cope with VIPT caches.
319 */
320#define HAVE_ARCH_UNMAPPED_AREA
321#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
322
323#endif /* !__ASSEMBLY__ */
324
325#endif /* CONFIG_MMU */
326
327#endif /* _ASMARM_PGTABLE_H */