| 1 | /* SPDX-License-Identifier: GPL-2.0-only */
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| 2 | /*
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| 3 | * Copyright (C) 2010,2011 Google, Inc.
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| 4 | * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
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| 5 | *
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| 6 | * Author:
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| 7 | * Colin Cross <ccross@google.com>
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| 8 | * Erik Gilling <konkers@google.com>
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| 9 | * Doug Anderson <dianders@chromium.org>
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| 10 | * Stephen Warren <swarren@nvidia.com>
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| 11 | *
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| 12 | * Portions based on mach-omap2's debug-macro.S
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| 13 | * Copyright (C) 1994-1999 Russell King
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| 14 | */
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| 15 |
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| 16 | #include <linux/serial_reg.h>
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| 17 |
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| 18 | #define UART_SHIFT 2
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| 19 |
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| 20 | /* Physical addresses */
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| 21 | #define TEGRA_CLK_RESET_BASE 0x60006000
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| 22 | #define TEGRA_APB_MISC_BASE 0x70000000
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| 23 | #define TEGRA_UARTA_BASE 0x70006000
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| 24 | #define TEGRA_UARTB_BASE 0x70006040
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| 25 | #define TEGRA_UARTC_BASE 0x70006200
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| 26 | #define TEGRA_UARTD_BASE 0x70006300
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| 27 | #define TEGRA_UARTE_BASE 0x70006400
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| 28 | #define TEGRA_PMC_BASE 0x7000e400
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| 29 |
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| 30 | #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
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| 31 | #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
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| 32 | #define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
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| 33 | #define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
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| 34 | #define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
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| 35 | #define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
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| 36 | #define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
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| 37 | #define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
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| 38 |
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| 39 | /*
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| 40 | * Must be section-aligned since a section mapping is used early on.
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| 41 | * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
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| 42 | */
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| 43 | #define UART_VIRTUAL_BASE 0xfe800000
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| 44 |
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| 45 | #define checkuart(rp, rv, lhu, bit, uart) \
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| 46 | /* Load address of CLK_RST register */ \
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| 47 | ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
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| 48 | /* Load value from CLK_RST register */ \
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| 49 | ldr rp, [rp, #0] ; \
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| 50 | /* Test UART's reset bit */ \
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| 51 | tst rp, |
| 52 | /* If set, can't use UART; jump to save no UART */ \
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| 53 | bne 90f ; \
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| 54 | /* Load address of CLK_OUT_ENB register */ \
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| 55 | ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
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| 56 | /* Load value from CLK_OUT_ENB register */ \
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| 57 | ldr rp, [rp, #0] ; \
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| 58 | /* Test UART's clock enable bit */ \
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| 59 | tst rp, |
| 60 | /* If clear, can't use UART; jump to save no UART */ \
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| 61 | beq 90f ; \
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| 62 | /* Passed all tests, load address of UART registers */ \
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| 63 | ldr rp, =TEGRA_UART##uart##_BASE ; \
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| 64 | /* Jump to save UART address */ \
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| 65 | b 91f
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| 66 |
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| 67 | .macro addruart, rp, rv, tmp
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| 68 | adr \rp, 99f @ actual addr of 99f
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| 69 | ldr \rv, [\rp] @ linked addr is stored there
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| 70 | sub \rv, \rv, \rp @ offset between the two
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| 71 | ldr \rp, [\rp, #4] @ linked tegra_uart_config
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| 72 | sub \tmp, \rp, \rv @ actual tegra_uart_config
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| 73 | ldr \rp, [\tmp] @ Load tegra_uart_config
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| 74 | cmp \rp, #1 @ needs initialization?
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| 75 | bne 100f @ no; go load the addresses
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| 76 | mov \rv, #0 @ yes; record init is done
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| 77 | str \rv, [\tmp]
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| 78 |
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| 79 | #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
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| 80 | /* Check ODMDATA */
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| 81 | 10: ldr \rp, =TEGRA_PMC_SCRATCH20
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| 82 | ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
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| 83 | lsr \rv, \rp, #18 @ 19:18 are console type
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| 84 | and \rv, \rv, #3
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| 85 | cmp \rv, #2 @ 2 and 3 mean DCC, UART
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| 86 | beq 11f @ some boards swap the meaning
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| 87 | cmp \rv, #3 @ so accept either
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| 88 | bne 90f
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| 89 | 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
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| 90 | and \rv, #7
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| 91 | cmp \rv, #0 @ UART 0?
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| 92 | beq 20f
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| 93 | cmp \rv, #1 @ UART 1?
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| 94 | beq 21f
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| 95 | cmp \rv, #2 @ UART 2?
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| 96 | beq 22f
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| 97 | cmp \rv, #3 @ UART 3?
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| 98 | beq 23f
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| 99 | cmp \rv, #4 @ UART 4?
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| 100 | beq 24f
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| 101 | b 90f @ invalid
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| 102 | #endif
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| 103 |
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| 104 | #if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
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| 105 | defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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| 106 | /* Check UART A validity */
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| 107 | 20: checkuart(\rp, \rv, L, 6, A)
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| 108 | #endif
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| 109 |
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| 110 | #if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
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| 111 | defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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| 112 | /* Check UART B validity */
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| 113 | 21: checkuart(\rp, \rv, L, 7, B)
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| 114 | #endif
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| 115 |
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| 116 | #if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
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| 117 | defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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| 118 | /* Check UART C validity */
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| 119 | 22: checkuart(\rp, \rv, H, 23, C)
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| 120 | #endif
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| 121 |
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| 122 | #if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
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| 123 | defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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| 124 | /* Check UART D validity */
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| 125 | 23: checkuart(\rp, \rv, U, 1, D)
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| 126 | #endif
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| 127 |
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| 128 | #if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
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| 129 | defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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| 130 | /* Check UART E validity */
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| 131 | 24:
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| 132 | checkuart(\rp, \rv, U, 2, E)
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| 133 | #endif
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| 134 |
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| 135 | /* No valid UART found */
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| 136 | 90: mov \rp, #0
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| 137 | /* fall through */
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| 138 |
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| 139 | /* Record whichever UART we chose */
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| 140 | 91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
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| 141 | cmp \rp, #0 @ Valid UART address?
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| 142 | bne 92f @ Yes, go process it
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| 143 | str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
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| 144 | b 100f @ Done
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| 145 | 92: and \rv, \rp, #0xffffff @ offset within 1MB section
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| 146 | add \rv, \rv, #UART_VIRTUAL_BASE
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| 147 | str \rv, [\tmp, #8] @ Store in tegra_uart_virt
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| 148 | b 100f
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| 149 |
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| 150 | .align
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| 151 | 99: .word .
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| 152 | #if defined(ZIMAGE)
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| 153 | .word . + 4
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| 154 | /*
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| 155 | * Storage for the state maintained by the macro.
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| 156 | *
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| 157 | * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
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| 158 | * That's because this header is included from multiple files, and we only
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| 159 | * want a single copy of the data. In particular, the UART probing code above
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| 160 | * assumes it's running using physical addresses. This is true when this file
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| 161 | * is included from head.o, but not when included from debug.o. So we need
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| 162 | * to share the probe results between the two copies, rather than having
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| 163 | * to re-run the probing again later.
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| 164 | *
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| 165 | * In the decompressor, we put the storage right here, since common.c
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| 166 | * isn't included in the decompressor build. This storage data gets put in
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| 167 | * .text even though it's really data, since .data is discarded from the
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| 168 | * decompressor. Luckily, .text is writeable in the decompressor, unless
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| 169 | * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
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| 170 | */
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| 171 | /* Debug UART initialization required */
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| 172 | .word 1
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| 173 | /* Debug UART physical address */
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| 174 | .word 0
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| 175 | /* Debug UART virtual address */
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| 176 | .word 0
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| 177 | #else
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| 178 | .word tegra_uart_config
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| 179 | #endif
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| 180 | .ltorg
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| 181 |
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| 182 | /* Load previously selected UART address */
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| 183 | 100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
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| 184 | ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
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| 185 | .endm
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| 186 |
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| 187 | /*
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| 188 | * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
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| 189 | * check to make sure that the UART address is actually valid.
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| 190 | */
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| 191 |
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| 192 | .macro senduart, rd, rx
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| 193 | cmp \rx, #0
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| 194 | strbne \rd, [\rx, #UART_TX << UART_SHIFT]
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| 195 | 1001:
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| 196 | .endm
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| 197 |
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| 198 | .macro busyuart, rd, rx
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| 199 | cmp \rx, #0
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| 200 | beq 1002f
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| 201 | 1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
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| 202 | and \rd, \rd, #UART_LSR_THRE
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| 203 | teq \rd, #UART_LSR_THRE
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| 204 | bne 1001b
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| 205 | 1002:
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| 206 | .endm
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| 207 |
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| 208 | .macro waituartcts, rd, rx
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| 209 | cmp \rx, #0
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| 210 | beq 1002f
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| 211 | 1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
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| 212 | tst \rd, #UART_MSR_CTS
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| 213 | beq 1001b
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| 214 | 1002:
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| 215 | .endm
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| 216 |
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| 217 | .macro waituarttxrdy,rd,rx
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| 218 | .endm
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