| 1 |
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| 2 | |
| 3 | * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
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| 4 | *
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| 5 | * Copyright (C) 1996-2000 Russell King
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| 6 | * Copyright (C) 2012 ARM Ltd.
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| 7 |
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| 8 | #ifndef __ASSEMBLER__
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| 9 | #error "Only include this from assembly code"
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| 10 | #endif
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| 11 |
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| 12 | #ifndef __ASM_ASSEMBLER_H
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| 13 | #define __ASM_ASSEMBLER_H
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| 14 |
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| 15 | #include <linux/export.h>
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| 16 |
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| 17 | #include <asm/alternative.h>
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| 18 | #include <asm/asm-bug.h>
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| 19 | #include <asm/asm-extable.h>
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| 20 | #include <asm/asm-offsets.h>
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| 21 | #include <asm/cpufeature.h>
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| 22 | #include <asm/cputype.h>
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| 23 | #include <asm/debug-monitors.h>
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| 24 | #include <asm/page.h>
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| 25 | #include <asm/pgtable-hwdef.h>
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| 26 | #include <asm/ptrace.h>
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| 27 | #include <asm/thread_info.h>
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| 28 |
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| 29 | |
| 30 | * Provide a wxN alias for each wN register so what we can paste a xN
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| 31 | * reference after a 'w' to obtain the 32-bit version.
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| 32 |
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| 33 | .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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| 34 | wx\n .req w\n
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| 35 | .endr
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| 36 |
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| 37 | |
| 38 | * Save/restore interrupts.
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| 39 |
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| 40 | .macro save_and_disable_daif, flags
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| 41 | mrs \flags, daif
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| 42 | msr daifset, #0xf
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| 43 | .endm
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| 44 |
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| 45 | .macro save_and_disable_irq, flags
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| 46 | mrs \flags, daif
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| 47 | msr daifset, #3
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| 48 | .endm
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| 49 |
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| 50 | .macro restore_irq, flags
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| 51 | msr daif, \flags
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| 52 | .endm
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| 53 |
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| 54 | .macro disable_step_tsk, flgs, tmp
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| 55 | tbz \flgs, #TIF_SINGLESTEP, 9990f
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| 56 | mrs \tmp, mdscr_el1
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| 57 | bic \tmp, \tmp, #MDSCR_EL1_SS
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| 58 | msr mdscr_el1, \tmp
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| 59 | isb |
| 60 | 9990:
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| 61 | .endm
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| 62 |
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| 63 |
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| 64 | .macro enable_step_tsk, flgs, tmp
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| 65 | tbz \flgs, #TIF_SINGLESTEP, 9990f
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| 66 | mrs \tmp, mdscr_el1
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| 67 | orr \tmp, \tmp, #MDSCR_EL1_SS
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| 68 | msr mdscr_el1, \tmp
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| 69 | 9990:
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| 70 | .endm
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| 71 |
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| 72 | |
| 73 | * RAS Error Synchronization barrier
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| 74 |
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| 75 | .macro esb
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| 76 | #ifdef CONFIG_ARM64_RAS_EXTN
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| 77 | hint #16
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| 78 | #else
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| 79 | nop
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| 80 | #endif
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| 81 | .endm
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| 82 |
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| 83 | |
| 84 | * Value prediction barrier
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| 85 |
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| 86 | .macro csdb
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| 87 | hint #20
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| 88 | .endm
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| 89 |
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| 90 | |
| 91 | * Clear Branch History instruction
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| 92 |
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| 93 | .macro clearbhb
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| 94 | hint #22
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| 95 | .endm
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| 96 |
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| 97 | |
| 98 | * Speculation barrier
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| 99 |
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| 100 | .macro sb
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| 101 | alternative_if_not ARM64_HAS_SB
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| 102 | dsb nsh
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| 103 | isb
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| 104 | alternative_else
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| 105 | SB_BARRIER_INSN
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| 106 | nop
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| 107 | alternative_endif
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| 108 | .endm
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| 109 |
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| 110 | |
| 111 | * NOP sequence
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| 112 |
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| 113 | .macro nops, num
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| 114 | .rept \num
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| 115 | nop
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| 116 | .endr
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| 117 | .endm
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| 118 |
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| 119 | |
| 120 | * Register aliases.
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| 121 |
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| 122 | lr .req x30 |
| 123 |
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| 124 | |
| 125 | * Vector entry
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| 126 |
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| 127 | .macro ventry label
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| 128 | .align 7
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| 129 | b \label
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| 130 | .endm
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| 131 |
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| 132 | |
| 133 | * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
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| 134 | * <symbol> is within the range +/- 4 GB of the PC.
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| 135 |
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| 136 | |
| 137 | * @dst: destination register (64 bit wide)
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| 138 | * @sym: name of the symbol
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| 139 |
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| 140 | .macro adr_l, dst, sym
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| 141 | adrp \dst, \sym
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| 142 | add \dst, \dst, :lo12:\sym
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| 143 | .endm
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| 144 |
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| 145 | |
| 146 | * @dst: destination register (32 or 64 bit wide)
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| 147 | * @sym: name of the symbol
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| 148 | * @tmp: optional 64-bit scratch register to be used if <dst> is a
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| 149 | * 32-bit wide register, in which case it cannot be used to hold
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| 150 | * the address
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| 151 |
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| 152 | .macro ldr_l, dst, sym, tmp=
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| 153 | .ifb \tmp
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| 154 | adrp \dst, \sym
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| 155 | ldr \dst, [\dst, :lo12:\sym]
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| 156 | .else
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| 157 | adrp \tmp, \sym
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| 158 | ldr \dst, [\tmp, :lo12:\sym]
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| 159 | .endif
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| 160 | .endm
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| 161 |
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| 162 | |
| 163 | * @src: source register (32 or 64 bit wide)
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| 164 | * @sym: name of the symbol
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| 165 | * @tmp: mandatory 64-bit scratch register to calculate the address
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| 166 | * while <src> needs to be preserved.
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| 167 |
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| 168 | .macro str_l, src, sym, tmp
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| 169 | adrp \tmp, \sym
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| 170 | str \src, [\tmp, :lo12:\sym]
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| 171 | .endm
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| 172 |
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| 173 | |
| 174 | * @dst: destination register
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| 175 |
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| 176 | #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
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| 177 | .macro get_this_cpu_offset, dst
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| 178 | mrs \dst, tpidr_el2
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| 179 | .endm
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| 180 | #else
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| 181 | .macro get_this_cpu_offset, dst
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| 182 | alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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| 183 | mrs \dst, tpidr_el1
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| 184 | alternative_else
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| 185 | mrs \dst, tpidr_el2
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| 186 | alternative_endif
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| 187 | .endm
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| 188 |
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| 189 | .macro set_this_cpu_offset, src
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| 190 | alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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| 191 | msr tpidr_el1, \src
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| 192 | alternative_else
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| 193 | msr tpidr_el2, \src
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| 194 | alternative_endif
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| 195 | .endm
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| 196 | #endif
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| 197 |
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| 198 | |
| 199 | * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
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| 200 | * @sym: The name of the per-cpu variable
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| 201 | * @tmp: scratch register
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| 202 |
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| 203 | .macro adr_this_cpu, dst, sym, tmp
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| 204 | adrp \tmp, \sym
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| 205 | add \dst, \tmp, #:lo12:\sym
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| 206 | get_this_cpu_offset \tmp
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| 207 | add \dst, \dst, \tmp
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| 208 | .endm
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| 209 |
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| 210 | |
| 211 | * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
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| 212 | * @sym: The name of the per-cpu variable
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| 213 | * @tmp: scratch register
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| 214 |
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| 215 | .macro ldr_this_cpu dst, sym, tmp
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| 216 | adr_l \dst, \sym
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| 217 | get_this_cpu_offset \tmp
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| 218 | ldr \dst, [\dst, \tmp]
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| 219 | .endm
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| 220 |
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| 221 | |
| 222 | * read_ctr - read CTR_EL0. If the system has mismatched register fields,
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| 223 | * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
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| 224 |
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| 225 | .macro read_ctr, reg
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| 226 | #ifndef __KVM_NVHE_HYPERVISOR__
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| 227 | alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
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| 228 | mrs \reg, ctr_el0 |
| 229 | nop
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| 230 | alternative_else
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| 231 | ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
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| 232 | alternative_endif
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| 233 | #else
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| 234 | alternative_if_not ARM64_KVM_PROTECTED_MODE
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| 235 | ASM_BUG()
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| 236 | alternative_else_nop_endif
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| 237 | alternative_cb ARM64_ALWAYS_SYSTEM, kvm_compute_final_ctr_el0
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| 238 | movz \reg, #0
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| 239 | movk \reg, #0, lsl #16
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| 240 | movk \reg, #0, lsl #32
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| 241 | movk \reg, #0, lsl #48
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| 242 | alternative_cb_end
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| 243 | #endif
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| 244 | .endm
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| 245 |
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| 246 |
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| 247 | |
| 248 | * raw_dcache_line_size - get the minimum D-cache line size on this CPU
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| 249 | * from the CTR register.
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| 250 |
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| 251 | .macro raw_dcache_line_size, reg, tmp
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| 252 | mrs \tmp, ctr_el0 |
| 253 | ubfm \tmp, \tmp, #16, #19 |
| 254 | mov \reg, #4 |
| 255 | lsl \reg, \reg, \tmp |
| 256 | .endm
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| 257 |
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| 258 | |
| 259 | * dcache_line_size - get the safe D-cache line size across all CPUs
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| 260 |
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| 261 | .macro dcache_line_size, reg, tmp
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| 262 | read_ctr \tmp
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| 263 | ubfm \tmp, \tmp, #16, #19 |
| 264 | mov \reg, #4 |
| 265 | lsl \reg, \reg, \tmp |
| 266 | .endm
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| 267 |
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| 268 | |
| 269 | * raw_icache_line_size - get the minimum I-cache line size on this CPU
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| 270 | * from the CTR register.
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| 271 |
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| 272 | .macro raw_icache_line_size, reg, tmp
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| 273 | mrs \tmp, ctr_el0 |
| 274 | and \tmp, \tmp, #0xf |
| 275 | mov \reg, #4 |
| 276 | lsl \reg, \reg, \tmp |
| 277 | .endm
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| 278 |
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| 279 | |
| 280 | * icache_line_size - get the safe I-cache line size across all CPUs
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| 281 |
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| 282 | .macro icache_line_size, reg, tmp
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| 283 | read_ctr \tmp
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| 284 | and \tmp, \tmp, #0xf |
| 285 | mov \reg, #4 |
| 286 | lsl \reg, \reg, \tmp |
| 287 | .endm
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| 288 |
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| 289 | |
| 290 | * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
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| 291 |
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| 292 | .macro tcr_set_t0sz, valreg, t0sz
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| 293 | bfi \valreg, \t0sz, #TCR_EL1_T0SZ_SHIFT, #TCR_EL1_T0SZ_WIDTH
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| 294 | .endm
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| 295 |
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| 296 | |
| 297 | * tcr_set_t1sz - update TCR.T1SZ
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| 298 |
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| 299 | .macro tcr_set_t1sz, valreg, t1sz
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| 300 | bfi \valreg, \t1sz, #TCR_EL1_T1SZ_SHIFT, #TCR_EL1_T1SZ_WIDTH
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| 301 | .endm
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| 302 |
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| 303 | |
| 304 | * tcr_compute_pa_size - set TCR.(I)PS to the highest supported
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| 305 | * ID_AA64MMFR0_EL1.PARange value
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| 306 | *
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| 307 | * tcr: register with the TCR_ELx value to be updated
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| 308 | * pos: IPS or PS bitfield position
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| 309 | * tmp{0,1}: temporary registers
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| 310 |
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| 311 | .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
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| 312 | mrs \tmp0, ID_AA64MMFR0_EL1
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| 313 | |
| 314 | ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3
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| 315 | mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX
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| 316 | #ifdef CONFIG_ARM64_LPA2
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| 317 | alternative_if_not ARM64_HAS_VA52
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| 318 | mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_48
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| 319 | alternative_else_nop_endif
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| 320 | #endif
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| 321 | cmp \tmp0, \tmp1
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| 322 | csel \tmp0, \tmp1, \tmp0, hi
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| 323 | bfi \tcr, \tmp0, \pos, #3
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| 324 | .endm
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| 325 |
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| 326 | .macro __dcache_op_workaround_clean_cache, op, addr
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| 327 | alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
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| 328 | dc \op, \addr
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| 329 | alternative_else
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| 330 | dc civac, \addr
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| 331 | alternative_endif
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| 332 | .endm
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| 333 |
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| 334 | |
| 335 | * Macro to perform a data cache maintenance for the interval
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| 336 | * [start, end) with dcache line size explicitly provided.
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| 337 | *
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| 338 | * op: operation passed to dc instruction
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| 339 | * start: starting virtual address of the region
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| 340 | * end: end virtual address of the region
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| 341 | * linesz: dcache line size
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| 342 | * fixup: optional label to branch to on user fault
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| 343 | * Corrupts: start, end, tmp
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| 344 |
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| 345 | .macro dcache_by_myline_op_nosync op, start, end, linesz, tmp, fixup
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| 346 | sub \tmp, \linesz, #1
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| 347 | bic \start, \start, \tmp
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| 348 | alternative_if ARM64_WORKAROUND_4311569
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| 349 | mov \tmp, \start
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| 350 | alternative_else_nop_endif
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| 351 | .Ldcache_op\@:
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| 352 | .ifc \op, cvau
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| 353 | __dcache_op_workaround_clean_cache \op, \start
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| 354 | .else
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| 355 | .ifc \op, cvac
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| 356 | __dcache_op_workaround_clean_cache \op, \start
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| 357 | .else
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| 358 | .ifc \op, cvap
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| 359 | sys 3, c7, c12, 1, \start |
| 360 | .else
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| 361 | .ifc \op, cvadp
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| 362 | sys 3, c7, c13, 1, \start |
| 363 | .else
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| 364 | dc \op, \start
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| 365 | .endif
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| 366 | .endif
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| 367 | .endif
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| 368 | .endif
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| 369 | add \start, \start, \linesz
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| 370 | cmp \start, \end
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| 371 | b.lo .Ldcache_op\@
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| 372 | alternative_if ARM64_WORKAROUND_4311569
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| 373 | .ifnc \op, cvau
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| 374 | mov \start, \tmp
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| 375 | mov \tmp, xzr
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| 376 | cbnz \start, .Ldcache_op\@
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| 377 | .endif
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| 378 | alternative_else_nop_endif
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| 379 |
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| 380 | _cond_uaccess_extable .Ldcache_op\@, \fixup
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| 381 | .endm
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| 382 |
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| 383 | |
| 384 | * Macro to perform a data cache maintenance for the interval
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| 385 | * [start, end) without waiting for completion
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| 386 | *
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| 387 | * op: operation passed to dc instruction
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| 388 | * start: starting virtual address of the region
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| 389 | * end: end virtual address of the region
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| 390 | * fixup: optional label to branch to on user fault
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| 391 | * Corrupts: start, end, tmp1, tmp2
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| 392 |
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| 393 | .macro dcache_by_line_op_nosync op, start, end, tmp1, tmp2, fixup
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| 394 | dcache_line_size \tmp1, \tmp2
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| 395 | dcache_by_myline_op_nosync \op, \start, \end, \tmp1, \tmp2, \fixup
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| 396 | .endm
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| 397 |
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| 398 | |
| 399 | * Macro to perform a data cache maintenance for the interval
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| 400 | * [start, end) and wait for completion
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| 401 | *
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| 402 | * op: operation passed to dc instruction
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| 403 | * domain: domain used in dsb instruction
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| 404 | * start: starting virtual address of the region
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| 405 | * end: end virtual address of the region
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| 406 | * fixup: optional label to branch to on user fault
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| 407 | * Corrupts: start, end, tmp1, tmp2
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| 408 |
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| 409 | .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
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| 410 | dcache_by_line_op_nosync \op, \start, \end, \tmp1, \tmp2, \fixup
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| 411 | dsb \domain
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| 412 | .endm
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| 413 |
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| 414 | |
| 415 | * Macro to perform an instruction cache maintenance for the interval
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| 416 | * [start, end)
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| 417 | *
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| 418 | * start, end: virtual addresses describing the region
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| 419 | * fixup: optional label to branch to on user fault
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| 420 | * Corrupts: tmp1, tmp2
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| 421 |
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| 422 | .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
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| 423 | alternative_if ARM64_WORKAROUND_NXP_ERR050104
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| 424 | ic ialluis
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| 425 | b .Licache_done\@
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| 426 | alternative_else_nop_endif
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| 427 | icache_line_size \tmp1, \tmp2
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| 428 | sub \tmp2, \tmp1, #1
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| 429 | bic \tmp2, \start, \tmp2
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| 430 | .Licache_op\@:
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| 431 | ic ivau, \tmp2 |
| 432 | add \tmp2, \tmp2, \tmp1
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| 433 | cmp \tmp2, \end
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| 434 | b.lo .Licache_op\@
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| 435 | .Licache_done\@:
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| 436 | dsb ish
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| 437 | isb
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| 438 |
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| 439 | _cond_uaccess_extable .Licache_op\@, \fixup
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| 440 | .endm
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| 441 |
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| 442 | |
| 443 | * load_ttbr1 - install @pgtbl as a TTBR1 page table
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| 444 | * pgtbl preserved
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| 445 | * tmp1/tmp2 clobbered, either may overlap with pgtbl
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| 446 |
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| 447 | .macro load_ttbr1, pgtbl, tmp1, tmp2
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| 448 | phys_to_ttbr \tmp1, \pgtbl
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| 449 | offset_ttbr1 \tmp1, \tmp2
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| 450 | msr ttbr1_el1, \tmp1
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| 451 | isb
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| 452 | .endm
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| 453 |
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| 454 | |
| 455 | * To prevent the possibility of old and new partial table walks being visible
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| 456 | * in the tlb, switch the ttbr to a zero page when we invalidate the old
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| 457 | * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
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| 458 | * Even switching to our copied tables will cause a changed output address at
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| 459 | * each stage of the walk.
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| 460 |
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| 461 | .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
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| 462 | phys_to_ttbr \tmp, \zero_page
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| 463 | msr ttbr1_el1, \tmp
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| 464 | isb
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| 465 | tlbi vmalle1
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| 466 | dsb nsh
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| 467 | load_ttbr1 \page_table, \tmp, \tmp2
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| 468 | .endm
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| 469 |
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| 470 | |
| 471 | * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
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| 472 |
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| 473 | .macro reset_pmuserenr_el0, tmpreg
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| 474 | mrs \tmpreg, id_aa64dfr0_el1
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| 475 | ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
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| 476 | cmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_NI
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| 477 | ccmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
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| 478 | b.eq 9000f |
| 479 | msr pmuserenr_el0, xzr |
| 480 | 9000:
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| 481 | .endm
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| 482 |
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| 483 | |
| 484 | * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present
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| 485 |
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| 486 | .macro reset_amuserenr_el0, tmpreg
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| 487 | mrs \tmpreg, id_aa64pfr0_el1 |
| 488 | ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
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| 489 | cbz \tmpreg, .Lskip_\@ |
| 490 | msr_s SYS_AMUSERENR_EL0, xzr |
| 491 | .Lskip_\@:
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| 492 | .endm
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| 493 | |
| 494 | * copy_page - copy src to dest using temp registers t1-t8
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| 495 |
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| 496 | .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
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| 497 | 9998: ldp \t1, \t2, [\src]
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| 498 | ldp \t3, \t4, [\src, #16]
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| 499 | ldp \t5, \t6, [\src, #32]
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| 500 | ldp \t7, \t8, [\src, #48]
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| 501 | add \src, \src, #64
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| 502 | stnp \t1, \t2, [\dest]
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| 503 | stnp \t3, \t4, [\dest, #16]
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| 504 | stnp \t5, \t6, [\dest, #32]
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| 505 | stnp \t7, \t8, [\dest, #48]
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| 506 | add \dest, \dest, #64
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| 507 | tst \src, #(PAGE_SIZE - 1)
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| 508 | b.ne 9998b
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| 509 | .endm
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| 510 |
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| 511 | |
| 512 | * Annotate a function as being unsuitable for kprobes.
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| 513 |
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| 514 | #ifdef CONFIG_KPROBES
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| 515 | #define NOKPROBE(x) \
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| 516 | .pushsection "_kprobe_blacklist", "aw"; \
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| 517 | .quad x; \
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| 518 | .popsection;
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| 519 | #else
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| 520 | #define NOKPROBE(x)
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| 521 | #endif
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| 522 |
|
| 523 | #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
|
| 524 | #define EXPORT_SYMBOL_NOKASAN(name)
|
| 525 | #else
|
| 526 | #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
|
| 527 | #endif
|
| 528 |
|
| 529 | |
| 530 | * Emit a 64-bit absolute little endian symbol reference in a way that
|
| 531 | * ensures that it will be resolved at build time, even when building a
|
| 532 | * PIE binary. This requires cooperation from the linker script, which
|
| 533 | * must emit the lo32/hi32 halves individually.
|
| 534 |
|
| 535 | .macro le64sym, sym
|
| 536 | .long \sym\()_lo32
|
| 537 | .long \sym\()_hi32
|
| 538 | .endm
|
| 539 |
|
| 540 | |
| 541 | * mov_q - move an immediate constant into a 64-bit register using
|
| 542 | * between 2 and 4 movz/movk instructions (depending on the
|
| 543 | * magnitude and sign of the operand)
|
| 544 |
|
| 545 | .macro mov_q, reg, val
|
| 546 | .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
|
| 547 | movz \reg, :abs_g1_s:\val
|
| 548 | .else
|
| 549 | .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
|
| 550 | movz \reg, :abs_g2_s:\val
|
| 551 | .else
|
| 552 | movz \reg, :abs_g3:\val
|
| 553 | movk \reg, :abs_g2_nc:\val
|
| 554 | .endif
|
| 555 | movk \reg, :abs_g1_nc:\val
|
| 556 | .endif
|
| 557 | movk \reg, :abs_g0_nc:\val
|
| 558 | .endm
|
| 559 |
|
| 560 | |
| 561 | * Return the current task_struct.
|
| 562 |
|
| 563 | .macro get_current_task, rd
|
| 564 | mrs \rd, sp_el0
|
| 565 | .endm
|
| 566 |
|
| 567 | |
| 568 | * If the kernel is built for 52-bit virtual addressing but the hardware only
|
| 569 | * supports 48 bits, we cannot program the pgdir address into TTBR1 directly,
|
| 570 | * but we have to add an offset so that the TTBR1 address corresponds with the
|
| 571 | * pgdir entry that covers the lowest 48-bit addressable VA.
|
| 572 | *
|
| 573 | * Note that this trick is only used for LVA/64k pages - LPA2/4k pages uses an
|
| 574 | * additional paging level, and on LPA2/16k pages, we would end up with a root
|
| 575 | * level table with only 2 entries, which is suboptimal in terms of TLB
|
| 576 | * utilization, so there we fall back to 47 bits of translation if LPA2 is not
|
| 577 | * supported.
|
| 578 | *
|
| 579 | * orr is used as it can cover the immediate value (and is idempotent).
|
| 580 | * ttbr: Value of ttbr to set, modified.
|
| 581 |
|
| 582 | .macro offset_ttbr1, ttbr, tmp
|
| 583 | #if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2)
|
| 584 | mrs \tmp, tcr_el1
|
| 585 | and \tmp, \tmp, #TCR_EL1_T1SZ_MASK
|
| 586 | cmp \tmp, #TCR_T1SZ(VA_BITS_MIN)
|
| 587 | orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET
|
| 588 | csel \ttbr, \tmp, \ttbr, eq
|
| 589 | #endif
|
| 590 | .endm
|
| 591 |
|
| 592 | |
| 593 | * Arrange a physical address in a TTBR register, taking care of 52-bit
|
| 594 | * addresses.
|
| 595 | *
|
| 596 | * phys: physical address, preserved
|
| 597 | * ttbr: returns the TTBR value
|
| 598 |
|
| 599 | .macro phys_to_ttbr, ttbr, phys
|
| 600 | #ifdef CONFIG_ARM64_PA_BITS_52
|
| 601 | orr \ttbr, \phys, \phys, lsr #46
|
| 602 | and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
|
| 603 | #else
|
| 604 | mov \ttbr, \phys
|
| 605 | #endif
|
| 606 | .endm
|
| 607 |
|
| 608 | .macro phys_to_pte, pte, phys
|
| 609 | #ifdef CONFIG_ARM64_PA_BITS_52
|
| 610 | orr \pte, \phys, \phys, lsr #PTE_ADDR_HIGH_SHIFT
|
| 611 | and \pte, \pte, #PHYS_TO_PTE_ADDR_MASK
|
| 612 | #else
|
| 613 | mov \pte, \phys
|
| 614 | #endif
|
| 615 | .endm
|
| 616 |
|
| 617 | |
| 618 | * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
|
| 619 |
|
| 620 | .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
|
| 621 | #ifdef CONFIG_FUJITSU_ERRATUM_010001
|
| 622 | mrs \tmp1, midr_el1
|
| 623 |
|
| 624 | mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
|
| 625 | and \tmp1, \tmp1, \tmp2
|
| 626 | mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
|
| 627 | cmp \tmp1, \tmp2
|
| 628 | b.ne 10f
|
| 629 |
|
| 630 | mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
|
| 631 | bic \tcr, \tcr, \tmp2
|
| 632 | 10:
|
| 633 | #endif
|
| 634 | .endm
|
| 635 |
|
| 636 | |
| 637 | * Errata workaround prior to disable MMU. Insert an ISB immediately prior
|
| 638 | * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
|
| 639 |
|
| 640 | .macro pre_disable_mmu_workaround
|
| 641 | #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
|
| 642 | isb
|
| 643 | #endif
|
| 644 | .endm
|
| 645 |
|
| 646 | |
| 647 | * frame_push - Push @regcount callee saved registers to the stack,
|
| 648 | * starting at x19, as well as x29/x30, and set x29 to
|
| 649 | * the new value of sp. Add @extra bytes of stack space
|
| 650 | * for locals.
|
| 651 |
|
| 652 | .macro frame_push, regcount:req, extra
|
| 653 | __frame st, \regcount, \extra
|
| 654 | .endm
|
| 655 |
|
| 656 | |
| 657 | * frame_pop - Pop the callee saved registers from the stack that were
|
| 658 | * pushed in the most recent call to frame_push, as well
|
| 659 | * as x29/x30 and any extra stack space that may have been
|
| 660 | * allocated.
|
| 661 |
|
| 662 | .macro frame_pop
|
| 663 | __frame ld
|
| 664 | .endm
|
| 665 |
|
| 666 | .macro __frame_regs, reg1, reg2, op, num
|
| 667 | .if .Lframe_regcount == \num
|
| 668 | \op\()r \reg1, [sp, #(\num + 1) * 8]
|
| 669 | .elseif .Lframe_regcount > \num
|
| 670 | \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
|
| 671 | .endif
|
| 672 | .endm
|
| 673 |
|
| 674 | .macro __frame, op, regcount, extra=0
|
| 675 | .ifc \op, st
|
| 676 | .if (\regcount) < 0 || (\regcount) > 10
|
| 677 | .error "regcount should be in the range [0 ... 10]"
|
| 678 | .endif
|
| 679 | .if ((\extra) % 16) != 0
|
| 680 | .error "extra should be a multiple of 16 bytes"
|
| 681 | .endif
|
| 682 | .ifdef .Lframe_regcount
|
| 683 | .if .Lframe_regcount != -1
|
| 684 | .error "frame_push/frame_pop may not be nested"
|
| 685 | .endif
|
| 686 | .endif
|
| 687 | .set .Lframe_regcount, \regcount
|
| 688 | .set .Lframe_extra, \extra
|
| 689 | .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
|
| 690 | stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
|
| 691 | mov x29, sp
|
| 692 | .endif
|
| 693 |
|
| 694 | __frame_regs x19, x20, \op, 1
|
| 695 | __frame_regs x21, x22, \op, 3
|
| 696 | __frame_regs x23, x24, \op, 5
|
| 697 | __frame_regs x25, x26, \op, 7
|
| 698 | __frame_regs x27, x28, \op, 9
|
| 699 |
|
| 700 | .ifc \op, ld
|
| 701 | .if .Lframe_regcount == -1
|
| 702 | .error "frame_push/frame_pop may not be nested"
|
| 703 | .endif
|
| 704 | ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
|
| 705 | .set .Lframe_regcount, -1
|
| 706 | .endif
|
| 707 | .endm
|
| 708 |
|
| 709 | |
| 710 | * Set SCTLR_ELx to the @reg value, and invalidate the local icache
|
| 711 | * in the process. This is called when setting the MMU on.
|
| 712 |
|
| 713 | .macro set_sctlr, sreg, reg
|
| 714 | msr \sreg, \reg
|
| 715 | isb
|
| 716 | |
| 717 | * Invalidate the local I-cache so that any instructions fetched
|
| 718 | * speculatively from the PoC are discarded, since they may have
|
| 719 | * been dynamically patched at the PoU.
|
| 720 |
|
| 721 | ic iallu
|
| 722 | dsb nsh
|
| 723 | isb
|
| 724 | .endm
|
| 725 |
|
| 726 | .macro set_sctlr_el1, reg
|
| 727 | set_sctlr sctlr_el1, \reg
|
| 728 | .endm
|
| 729 |
|
| 730 | .macro set_sctlr_el2, reg
|
| 731 | set_sctlr sctlr_el2, \reg
|
| 732 | .endm
|
| 733 |
|
| 734 | |
| 735 | * Branch Target Identifier (BTI)
|
| 736 |
|
| 737 | .macro bti, targets
|
| 738 | .equ .L__bti_targets_c, 34
|
| 739 | .equ .L__bti_targets_j, 36
|
| 740 | .equ .L__bti_targets_jc,38
|
| 741 | hint #.L__bti_targets_\targets
|
| 742 | .endm
|
| 743 |
|
| 744 | |
| 745 | * This macro emits a program property note section identifying
|
| 746 | * architecture features which require special handling, mainly for
|
| 747 | * use in assembly files included in the VDSO.
|
| 748 |
|
| 749 |
|
| 750 | #define NT_GNU_PROPERTY_TYPE_0 5
|
| 751 | #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
|
| 752 |
|
| 753 | #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
|
| 754 | #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
|
| 755 |
|
| 756 | #ifdef CONFIG_ARM64_BTI_KERNEL
|
| 757 | #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \
|
| 758 | ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \
|
| 759 | GNU_PROPERTY_AARCH64_FEATURE_1_PAC))
|
| 760 | #endif
|
| 761 |
|
| 762 | #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
|
| 763 | .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
|
| 764 | .pushsection .note.gnu.property, "a"
|
| 765 | .align 3
|
| 766 | .long 2f - 1f
|
| 767 | .long 6f - 3f
|
| 768 | .long NT_GNU_PROPERTY_TYPE_0
|
| 769 | 1: .string "GNU"
|
| 770 | 2:
|
| 771 | .align 3
|
| 772 | 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND
|
| 773 | .long 5f - 4f
|
| 774 | 4:
|
| 775 | |
| 776 | * This is described with an array of char in the Linux API
|
| 777 | * spec but the text and all other usage (including binutils,
|
| 778 | * clang and GCC) treat this as a 32 bit value so no swizzling
|
| 779 | * is required for big endian.
|
| 780 |
|
| 781 | .long \feat
|
| 782 | 5:
|
| 783 | .align 3
|
| 784 | 6:
|
| 785 | .popsection
|
| 786 | .endm
|
| 787 |
|
| 788 | #else
|
| 789 | .macro emit_aarch64_feature_1_and, feat=0
|
| 790 | .endm
|
| 791 |
|
| 792 | #endif
|
| 793 |
|
| 794 | .macro __mitigate_spectre_bhb_loop tmp
|
| 795 | #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
| 796 | alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_iter
|
| 797 | mov \tmp, #32 |
| 798 | alternative_cb_end
|
| 799 | .Lspectre_bhb_loop\@:
|
| 800 | b . + 4
|
| 801 | subs \tmp, \tmp, #1
|
| 802 | b.ne .Lspectre_bhb_loop\@
|
| 803 | sb
|
| 804 | #endif
|
| 805 | .endm
|
| 806 |
|
| 807 | .macro mitigate_spectre_bhb_loop tmp
|
| 808 | #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
| 809 | alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_loop_mitigation_enable
|
| 810 | b .L_spectre_bhb_loop_done\@ |
| 811 | alternative_cb_end
|
| 812 | __mitigate_spectre_bhb_loop \tmp
|
| 813 | .L_spectre_bhb_loop_done\@:
|
| 814 | #endif
|
| 815 | .endm
|
| 816 |
|
| 817 |
|
| 818 | .macro __mitigate_spectre_bhb_fw
|
| 819 | #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
| 820 | stp x0, x1, [sp, #-16]!
|
| 821 | stp x2, x3, [sp, #-16]!
|
| 822 | mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3
|
| 823 | alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit
|
| 824 | nop |
| 825 | alternative_cb_end
|
| 826 | ldp x2, x3, [sp], #16
|
| 827 | ldp x0, x1, [sp], #16
|
| 828 | #endif
|
| 829 | .endm
|
| 830 |
|
| 831 | .macro mitigate_spectre_bhb_clear_insn
|
| 832 | #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
|
| 833 | alternative_cb ARM64_ALWAYS_SYSTEM, spectre_bhb_patch_clearbhb
|
| 834 |
|
| 835 | clearbhb
|
| 836 | isb
|
| 837 | alternative_cb_end
|
| 838 | #endif
|
| 839 | .endm
|
| 840 | #endif
|