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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5#ifndef __ASM_CACHE_H
6#define __ASM_CACHE_H
7
8#define L1_CACHE_SHIFT (6)
9#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
10
11#define CLIDR_LOUU_SHIFT 27
12#define CLIDR_LOC_SHIFT 24
13#define CLIDR_LOUIS_SHIFT 21
14
15#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
16#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
17#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
18
19/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
20#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
21#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
22#define CLIDR_CTYPE(clidr, level) \
23 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
24
25/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */
26#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT)
27
28/*
29 * Memory returned by kmalloc() may be used for DMA, so we must make
30 * sure that all such allocations are cache aligned. Otherwise,
31 * unrelated code may cause parts of the buffer to be read into the
32 * cache before the transfer is done, causing old data to be seen by
33 * the CPU.
34 */
35#define ARCH_DMA_MINALIGN (128)
36#define ARCH_KMALLOC_MINALIGN (8)
37
38#if !defined(__ASSEMBLER__) && !defined(BUILD_VDSO)
39
40#include <linux/bitops.h>
41#include <linux/kasan-enabled.h>
42
43#include <asm/cputype.h>
44#include <asm/mte-def.h>
45#include <asm/sysreg.h>
46
47#ifdef CONFIG_KASAN_SW_TAGS
48#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
49#elif defined(CONFIG_KASAN_HW_TAGS)
50static inline unsigned int arch_slab_minalign(void)
51{
52 return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
53 __alignof__(unsigned long long);
54}
55#define arch_slab_minalign() arch_slab_minalign()
56#endif
57
58#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
59
60#define ICACHEF_ALIASING 0
61extern unsigned long __icache_flags;
62
63/*
64 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
65 * permitted in the I-cache.
66 */
67static inline int icache_is_aliasing(void)
68{
69 return test_bit(ICACHEF_ALIASING, &__icache_flags);
70}
71
72static inline u32 cache_type_cwg(void)
73{
74 return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
75}
76
77#define __read_mostly __section(".data..read_mostly")
78
79static inline int cache_line_size_of_cpu(void)
80{
81 u32 cwg = cache_type_cwg();
82
83 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
84}
85
86int cache_line_size(void);
87
88#define dma_get_cache_alignment cache_line_size
89
90static inline void arch_sync_dma_flush(void)
91{
92 dsb(sy);
93}
94
95/* Compress a u64 MPIDR value into 32 bits. */
96static inline u64 arch_compact_of_hwid(u64 id)
97{
98 u64 aff3 = MPIDR_AFFINITY_LEVEL(id, 3);
99
100 /*
101 * These bits are expected to be RES0. If not, return a value with
102 * the upper 32 bits set to force the caller to give up on 32 bit
103 * cache ids.
104 */
105 if (FIELD_GET(GENMASK_ULL(63, 40), id))
106 return id;
107
108 return (aff3 << 24) | FIELD_GET(GENMASK_ULL(23, 0), id);
109}
110#define arch_compact_of_hwid arch_compact_of_hwid
111
112/*
113 * Read the effective value of CTR_EL0.
114 *
115 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
116 * section D10.2.33 "CTR_EL0, Cache Type Register" :
117 *
118 * CTR_EL0.IDC reports the data cache clean requirements for
119 * instruction to data coherence.
120 *
121 * 0 - dcache clean to PoU is required unless :
122 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
123 * 1 - dcache clean to PoU is not required for i-to-d coherence.
124 *
125 * This routine provides the CTR_EL0 with the IDC field updated to the
126 * effective state.
127 */
128static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
129{
130 u32 ctr = read_cpuid_cachetype();
131
132 if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
133 u64 clidr = read_sysreg(clidr_el1);
134
135 if (CLIDR_LOC(clidr) == 0 ||
136 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
137 ctr |= BIT(CTR_EL0_IDC_SHIFT);
138 }
139
140 return ctr;
141}
142
143#endif /* !defined(__ASSEMBLER__) && !defined(BUILD_VDSO) */
144
145#endif