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| 2 | |
| 3 | * Copyright (C) 2012 ARM Ltd.
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| 4 |
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| 5 | #ifndef __ASM_MODULE_H
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| 6 | #define __ASM_MODULE_H
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| 7 |
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| 8 | #include <asm-generic/module.h>
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| 9 |
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| 10 | struct mod_plt_sec {
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| 11 | int plt_shndx;
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| 12 | int plt_num_entries;
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| 13 | int plt_max_entries;
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| 14 | };
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| 15 |
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| 16 | struct mod_arch_specific {
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| 17 | struct mod_plt_sec core;
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| 18 | struct mod_plt_sec init;
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| 19 |
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| 20 |
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| 21 | struct plt_entry *ftrace_trampolines;
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| 22 | struct plt_entry *init_ftrace_trampolines;
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| 23 | };
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| 24 |
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| 25 | u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs,
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| 26 | void *loc, const Elf64_Rela *rela,
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| 27 | Elf64_Sym *sym);
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| 28 |
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| 29 | u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs,
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| 30 | void *loc, u64 val);
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| 31 |
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| 32 | struct plt_entry {
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| 33 | |
| 34 | * A program that conforms to the AArch64 Procedure Call Standard
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| 35 | * (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
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| 36 | * IP1 (x17) may be inserted at any branch instruction that is
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| 37 | * exposed to a relocation that supports long branches. Since that
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| 38 | * is exactly what we are dealing with here, we are free to use x16
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| 39 | * as a scratch register in the PLT veneers.
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| 40 |
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| 41 | __le32 adrp;
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| 42 | __le32 add;
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| 43 | __le32 br;
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| 44 | };
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| 45 |
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| 46 | static inline bool is_forbidden_offset_for_adrp(void *place)
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| 47 | {
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| 48 | return cpus_have_final_cap(ARM64_WORKAROUND_843419) &&
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| 49 | ((u64)place & 0xfff) >= 0xff8;
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| 50 | }
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| 51 |
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| 52 | struct plt_entry get_plt_entry(u64 dst, void *pc);
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| 53 |
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| 54 | static inline const Elf_Shdr *find_section(const Elf_Ehdr *hdr,
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| 55 | const Elf_Shdr *sechdrs,
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| 56 | const char *name)
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| 57 | {
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| 58 | const Elf_Shdr *s, *se;
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| 59 | const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
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| 60 |
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| 61 | for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
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| 62 | if (strcmp(name, secstrs + s->sh_name) == 0)
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| 63 | return s;
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| 64 | }
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| 65 |
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| 66 | return NULL;
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| 67 | }
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| 68 |
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| 69 | #endif
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