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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020 ARM Ltd.
4 */
5
6#include <linux/bitops.h>
7#include <linux/cpu.h>
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/prctl.h>
11#include <linux/ptrace.h>
12#include <linux/sched.h>
13#include <linux/sched/mm.h>
14#include <linux/string.h>
15#include <linux/swap.h>
16#include <linux/swapops.h>
17#include <linux/thread_info.h>
18#include <linux/types.h>
19#include <linux/uaccess.h>
20#include <linux/uio.h>
21
22#include <asm/barrier.h>
23#include <asm/cpufeature.h>
24#include <asm/mte.h>
25#include <asm/ptrace.h>
26#include <asm/sysreg.h>
27
28static DEFINE_PER_CPU_READ_MOSTLY(u64, mte_tcf_preferred);
29
30#ifdef CONFIG_KASAN_HW_TAGS
31/*
32 * The asynchronous and asymmetric MTE modes have the same behavior for
33 * store operations. This flag is set when either of these modes is enabled.
34 */
35DEFINE_STATIC_KEY_FALSE(mte_async_or_asymm_mode);
36EXPORT_SYMBOL_GPL(mte_async_or_asymm_mode);
37#endif
38
39void mte_sync_tags(pte_t pte, unsigned int nr_pages)
40{
41 struct page *page = pte_page(pte);
42 struct folio *folio = page_folio(page);
43 unsigned long i;
44
45 if (folio_test_hugetlb(folio)) {
46 unsigned long nr = folio_nr_pages(folio);
47
48 /* Hugetlb MTE flags are set for head page only */
49 if (folio_try_hugetlb_mte_tagging(folio)) {
50 for (i = 0; i < nr; i++, page++)
51 mte_clear_page_tags(page_address(page));
52 folio_set_hugetlb_mte_tagged(folio);
53 }
54
55 /* ensure the tags are visible before the PTE is set */
56 smp_wmb();
57
58 return;
59 }
60
61 /* if PG_mte_tagged is set, tags have already been initialised */
62 for (i = 0; i < nr_pages; i++, page++) {
63 if (try_page_mte_tagging(page)) {
64 mte_clear_page_tags(page_address(page));
65 set_page_mte_tagged(page);
66 }
67 }
68
69 /* ensure the tags are visible before the PTE is set */
70 smp_wmb();
71}
72
73int memcmp_pages(struct page *page1, struct page *page2)
74{
75 char *addr1, *addr2;
76 int ret;
77
78 addr1 = page_address(page1);
79 addr2 = page_address(page2);
80 ret = memcmp(addr1, addr2, PAGE_SIZE);
81
82 if (!system_supports_mte() || ret)
83 return ret;
84
85 /*
86 * If the page content is identical but at least one of the pages is
87 * tagged, return non-zero to avoid KSM merging. If only one of the
88 * pages is tagged, __set_ptes() may zero or change the tags of the
89 * other page via mte_sync_tags().
90 */
91 if (page_mte_tagged(page1) || page_mte_tagged(page2))
92 return addr1 != addr2;
93
94 return ret;
95}
96
97static inline void __mte_enable_kernel(const char *mode, unsigned long tcf)
98{
99 /* Enable MTE Sync Mode for EL1. */
100 sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK,
101 SYS_FIELD_PREP(SCTLR_EL1, TCF, tcf));
102 isb();
103
104 pr_info_once("MTE: enabled in %s mode at EL1\n", mode);
105}
106
107#ifdef CONFIG_KASAN_HW_TAGS
108void mte_enable_kernel_sync(void)
109{
110 /*
111 * Make sure we enter this function when no PE has set
112 * async mode previously.
113 */
114 WARN_ONCE(system_uses_mte_async_or_asymm_mode(),
115 "MTE async mode enabled system wide!");
116
117 __mte_enable_kernel("synchronous", SCTLR_EL1_TCF_SYNC);
118}
119
120void mte_enable_kernel_async(void)
121{
122 __mte_enable_kernel("asynchronous", SCTLR_EL1_TCF_ASYNC);
123
124 /*
125 * MTE async mode is set system wide by the first PE that
126 * executes this function.
127 *
128 * Note: If in future KASAN acquires a runtime switching
129 * mode in between sync and async, this strategy needs
130 * to be reviewed.
131 */
132 if (!system_uses_mte_async_or_asymm_mode())
133 static_branch_enable(&mte_async_or_asymm_mode);
134}
135
136void mte_enable_kernel_asymm(void)
137{
138 if (cpus_have_cap(ARM64_MTE_ASYMM)) {
139 __mte_enable_kernel("asymmetric", SCTLR_EL1_TCF_ASYMM);
140
141 /*
142 * MTE asymm mode behaves as async mode for store
143 * operations. The mode is set system wide by the
144 * first PE that executes this function.
145 *
146 * Note: If in future KASAN acquires a runtime switching
147 * mode in between sync and async, this strategy needs
148 * to be reviewed.
149 */
150 if (!system_uses_mte_async_or_asymm_mode())
151 static_branch_enable(&mte_async_or_asymm_mode);
152 } else {
153 /*
154 * If the CPU does not support MTE asymmetric mode the
155 * kernel falls back on synchronous mode which is the
156 * default for kasan=on.
157 */
158 mte_enable_kernel_sync();
159 }
160}
161
162int mte_enable_kernel_store_only(void)
163{
164 /*
165 * If the CPU does not support MTE store only,
166 * the kernel checks all operations.
167 */
168 if (!cpus_have_cap(ARM64_MTE_STORE_ONLY))
169 return -EINVAL;
170
171 sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCSO_MASK,
172 SYS_FIELD_PREP(SCTLR_EL1, TCSO, 1));
173 isb();
174
175 pr_info_once("MTE: enabled store only mode at EL1\n");
176
177 return 0;
178}
179#endif
180
181#ifdef CONFIG_KASAN_HW_TAGS
182void mte_check_tfsr_el1(void)
183{
184 u64 tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1);
185
186 if (unlikely(tfsr_el1 & SYS_TFSR_EL1_TF1)) {
187 /*
188 * Note: isb() is not required after this direct write
189 * because there is no indirect read subsequent to it
190 * (per ARM DDI 0487F.c table D13-1).
191 */
192 write_sysreg_s(0, SYS_TFSR_EL1);
193
194 kasan_report_async();
195 }
196}
197#endif
198
199/*
200 * This is where we actually resolve the system and process MTE mode
201 * configuration into an actual value in SCTLR_EL1 that affects
202 * userspace.
203 */
204static void mte_update_sctlr_user(struct task_struct *task)
205{
206 /*
207 * This must be called with preemption disabled and can only be called
208 * on the current or next task since the CPU must match where the thread
209 * is going to run. The caller is responsible for calling
210 * update_sctlr_el1() later in the same preemption disabled block.
211 */
212 unsigned long sctlr = task->thread.sctlr_user;
213 unsigned long mte_ctrl = task->thread.mte_ctrl;
214 unsigned long pref, resolved_mte_tcf;
215
216 pref = __this_cpu_read(mte_tcf_preferred);
217 /*
218 * If there is no overlap between the system preferred and
219 * program requested values go with what was requested.
220 */
221 resolved_mte_tcf = (mte_ctrl & pref) ? pref : mte_ctrl;
222 sctlr &= ~(SCTLR_EL1_TCF0_MASK | SCTLR_EL1_TCSO0_MASK);
223 /*
224 * Pick an actual setting. The order in which we check for
225 * set bits and map into register values determines our
226 * default order.
227 */
228 if (resolved_mte_tcf & MTE_CTRL_TCF_ASYMM)
229 sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYMM);
230 else if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC)
231 sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYNC);
232 else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC)
233 sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, SYNC);
234
235 if (mte_ctrl & MTE_CTRL_STORE_ONLY)
236 sctlr |= SYS_FIELD_PREP(SCTLR_EL1, TCSO0, 1);
237
238 task->thread.sctlr_user = sctlr;
239}
240
241static void mte_update_gcr_excl(struct task_struct *task)
242{
243 /*
244 * SYS_GCR_EL1 will be set to current->thread.mte_ctrl value by
245 * mte_set_user_gcr() in kernel_exit, but only if KASAN is enabled.
246 */
247 if (kasan_hw_tags_enabled())
248 return;
249
250 write_sysreg_s(
251 ((task->thread.mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) &
252 SYS_GCR_EL1_EXCL_MASK) | SYS_GCR_EL1_RRND,
253 SYS_GCR_EL1);
254}
255
256#ifdef CONFIG_KASAN_HW_TAGS
257/* Only called from assembly, silence sparse */
258void __init kasan_hw_tags_enable(struct alt_instr *alt, __le32 *origptr,
259 __le32 *updptr, int nr_inst);
260
261void __init kasan_hw_tags_enable(struct alt_instr *alt, __le32 *origptr,
262 __le32 *updptr, int nr_inst)
263{
264 BUG_ON(nr_inst != 1); /* Branch -> NOP */
265
266 if (kasan_hw_tags_enabled())
267 *updptr = cpu_to_le32(aarch64_insn_gen_nop());
268}
269#endif
270
271void mte_thread_init_user(void)
272{
273 if (!system_supports_mte())
274 return;
275
276 /* clear any pending asynchronous tag fault */
277 dsb(ish);
278 write_sysreg_s(0, SYS_TFSRE0_EL1);
279 clear_thread_flag(TIF_MTE_ASYNC_FAULT);
280 /* disable tag checking and reset tag generation mask */
281 set_mte_ctrl(current, 0);
282}
283
284void mte_thread_switch(struct task_struct *next)
285{
286 if (!system_supports_mte())
287 return;
288
289 mte_update_sctlr_user(next);
290 mte_update_gcr_excl(next);
291
292 /* TCO may not have been disabled on exception entry for the current task. */
293 mte_disable_tco_entry(next);
294
295 if (!system_uses_mte_async_or_asymm_mode())
296 return;
297
298 /*
299 * Check if an async tag exception occurred at EL1.
300 *
301 * Note: On the context switch path we rely on the dsb() present
302 * in __switch_to() to guarantee that the indirect writes to TFSR_EL1
303 * are synchronized before this point.
304 */
305 isb();
306 mte_check_tfsr_el1();
307}
308
309void mte_cpu_setup(void)
310{
311 u64 rgsr;
312
313 /*
314 * CnP must be enabled only after the MAIR_EL1 register has been set
315 * up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may
316 * lead to the wrong memory type being used for a brief window during
317 * CPU power-up.
318 *
319 * CnP is not a boot feature so MTE gets enabled before CnP, but let's
320 * make sure that is the case.
321 */
322 BUG_ON(read_sysreg(ttbr0_el1) & TTBRx_EL1_CnP);
323 BUG_ON(read_sysreg(ttbr1_el1) & TTBRx_EL1_CnP);
324
325 /* Normal Tagged memory type at the corresponding MAIR index */
326 sysreg_clear_set(mair_el1,
327 MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED),
328 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_TAGGED,
329 MT_NORMAL_TAGGED));
330
331 write_sysreg_s(KERNEL_GCR_EL1, SYS_GCR_EL1);
332
333 /*
334 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
335 * RGSR_EL1.SEED must be non-zero for IRG to produce
336 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
337 * must initialize it.
338 */
339 rgsr = (read_sysreg(CNTVCT_EL0) & SYS_RGSR_EL1_SEED_MASK) <<
340 SYS_RGSR_EL1_SEED_SHIFT;
341 if (rgsr == 0)
342 rgsr = 1 << SYS_RGSR_EL1_SEED_SHIFT;
343 write_sysreg_s(rgsr, SYS_RGSR_EL1);
344
345 /* clear any pending tag check faults in TFSR*_EL1 */
346 write_sysreg_s(0, SYS_TFSR_EL1);
347 write_sysreg_s(0, SYS_TFSRE0_EL1);
348
349 local_flush_tlb_all();
350}
351
352void mte_suspend_enter(void)
353{
354 if (!system_supports_mte())
355 return;
356
357 if (!system_uses_mte_async_or_asymm_mode())
358 return;
359
360 /*
361 * The barriers are required to guarantee that the indirect writes
362 * to TFSR_EL1 are synchronized before we report the state.
363 */
364 dsb(nsh);
365 isb();
366
367 /* Report SYS_TFSR_EL1 before suspend entry */
368 mte_check_tfsr_el1();
369}
370
371void mte_suspend_exit(void)
372{
373 if (!system_supports_mte())
374 return;
375
376 mte_cpu_setup();
377}
378
379long set_mte_ctrl(struct task_struct *task, unsigned long arg)
380{
381 u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &
382 SYS_GCR_EL1_EXCL_MASK) << MTE_CTRL_GCR_USER_EXCL_SHIFT;
383
384 if (!system_supports_mte())
385 return 0;
386
387 if (arg & PR_MTE_TCF_ASYNC)
388 mte_ctrl |= MTE_CTRL_TCF_ASYNC;
389 if (arg & PR_MTE_TCF_SYNC)
390 mte_ctrl |= MTE_CTRL_TCF_SYNC;
391
392 /*
393 * If the system supports it and both sync and async modes are
394 * specified then implicitly enable asymmetric mode.
395 * Userspace could see a mix of both sync and async anyway due
396 * to differing or changing defaults on CPUs.
397 */
398 if (cpus_have_cap(ARM64_MTE_ASYMM) &&
399 (arg & PR_MTE_TCF_ASYNC) &&
400 (arg & PR_MTE_TCF_SYNC))
401 mte_ctrl |= MTE_CTRL_TCF_ASYMM;
402
403 if (arg & PR_MTE_STORE_ONLY)
404 mte_ctrl |= MTE_CTRL_STORE_ONLY;
405
406 task->thread.mte_ctrl = mte_ctrl;
407 if (task == current) {
408 preempt_disable();
409 mte_update_sctlr_user(task);
410 mte_update_gcr_excl(task);
411 update_sctlr_el1(task->thread.sctlr_user);
412 preempt_enable();
413 }
414
415 return 0;
416}
417
418long get_mte_ctrl(struct task_struct *task)
419{
420 unsigned long ret;
421 u64 mte_ctrl = task->thread.mte_ctrl;
422 u64 incl = (~mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) &
423 SYS_GCR_EL1_EXCL_MASK;
424
425 if (!system_supports_mte())
426 return 0;
427
428 ret = incl << PR_MTE_TAG_SHIFT;
429 if (mte_ctrl & MTE_CTRL_TCF_ASYNC)
430 ret |= PR_MTE_TCF_ASYNC;
431 if (mte_ctrl & MTE_CTRL_TCF_SYNC)
432 ret |= PR_MTE_TCF_SYNC;
433 if (mte_ctrl & MTE_CTRL_STORE_ONLY)
434 ret |= PR_MTE_STORE_ONLY;
435
436 return ret;
437}
438
439/*
440 * Access MTE tags in another process' address space as given in mm. Update
441 * the number of tags copied. Return 0 if any tags copied, error otherwise.
442 * Inspired by __access_remote_vm().
443 */
444static int __access_remote_tags(struct mm_struct *mm, unsigned long addr,
445 struct iovec *kiov, unsigned int gup_flags)
446{
447 void __user *buf = kiov->iov_base;
448 size_t len = kiov->iov_len;
449 int err = 0;
450 int write = gup_flags & FOLL_WRITE;
451
452 if (!access_ok(buf, len))
453 return -EFAULT;
454
455 if (mmap_read_lock_killable(mm))
456 return -EIO;
457
458 while (len) {
459 struct vm_area_struct *vma;
460 unsigned long tags, offset;
461 void *maddr;
462 struct page *page = get_user_page_vma_remote(mm, addr,
463 gup_flags, &vma);
464 struct folio *folio;
465
466 if (IS_ERR(page)) {
467 err = PTR_ERR(page);
468 break;
469 }
470
471 /*
472 * Only copy tags if the page has been mapped as PROT_MTE
473 * (PG_mte_tagged set). Otherwise the tags are not valid and
474 * not accessible to user. Moreover, an mprotect(PROT_MTE)
475 * would cause the existing tags to be cleared if the page
476 * was never mapped with PROT_MTE.
477 */
478 if (!(vma->vm_flags & VM_MTE)) {
479 err = -EIO;
480 put_page(page);
481 break;
482 }
483
484 folio = page_folio(page);
485 if (folio_test_hugetlb(folio))
486 WARN_ON_ONCE(!folio_test_hugetlb_mte_tagged(folio) &&
487 !is_huge_zero_folio(folio));
488 else
489 WARN_ON_ONCE(!page_mte_tagged(page) && !is_zero_page(page));
490
491 /* limit access to the end of the page */
492 offset = offset_in_page(addr);
493 tags = min(len, (PAGE_SIZE - offset) / MTE_GRANULE_SIZE);
494
495 maddr = page_address(page);
496 if (write) {
497 tags = mte_copy_tags_from_user(maddr + offset, buf, tags);
498 set_page_dirty_lock(page);
499 } else {
500 tags = mte_copy_tags_to_user(buf, maddr + offset, tags);
501 }
502 put_page(page);
503
504 /* error accessing the tracer's buffer */
505 if (!tags)
506 break;
507
508 len -= tags;
509 buf += tags;
510 addr += tags * MTE_GRANULE_SIZE;
511 }
512 mmap_read_unlock(mm);
513
514 /* return an error if no tags copied */
515 kiov->iov_len = buf - kiov->iov_base;
516 if (!kiov->iov_len) {
517 /* check for error accessing the tracee's address space */
518 if (err)
519 return -EIO;
520 else
521 return -EFAULT;
522 }
523
524 return 0;
525}
526
527/*
528 * Copy MTE tags in another process' address space at 'addr' to/from tracer's
529 * iovec buffer. Return 0 on success. Inspired by ptrace_access_vm().
530 */
531static int access_remote_tags(struct task_struct *tsk, unsigned long addr,
532 struct iovec *kiov, unsigned int gup_flags)
533{
534 struct mm_struct *mm;
535 int ret;
536
537 mm = get_task_mm(tsk);
538 if (!mm)
539 return -EPERM;
540
541 if (!ptracer_access_allowed(tsk)) {
542 mmput(mm);
543 return -EPERM;
544 }
545
546 ret = __access_remote_tags(mm, addr, kiov, gup_flags);
547 mmput(mm);
548 return ret;
549}
550
551int mte_ptrace_copy_tags(struct task_struct *child, long request,
552 unsigned long addr, unsigned long data)
553{
554 int ret;
555 struct iovec kiov;
556 struct iovec __user *uiov = (void __user *)data;
557 unsigned int gup_flags = FOLL_FORCE;
558
559 if (!system_supports_mte())
560 return -EIO;
561
562 if (get_user(kiov.iov_base, &uiov->iov_base) ||
563 get_user(kiov.iov_len, &uiov->iov_len))
564 return -EFAULT;
565
566 if (request == PTRACE_POKEMTETAGS)
567 gup_flags |= FOLL_WRITE;
568
569 /* align addr to the MTE tag granule */
570 addr &= MTE_GRANULE_MASK;
571
572 ret = access_remote_tags(child, addr, &kiov, gup_flags);
573 if (!ret)
574 ret = put_user(kiov.iov_len, &uiov->iov_len);
575
576 return ret;
577}
578
579static ssize_t mte_tcf_preferred_show(struct device *dev,
580 struct device_attribute *attr, char *buf)
581{
582 switch (per_cpu(mte_tcf_preferred, dev->id)) {
583 case MTE_CTRL_TCF_ASYNC:
584 return sysfs_emit(buf, "async\n");
585 case MTE_CTRL_TCF_SYNC:
586 return sysfs_emit(buf, "sync\n");
587 case MTE_CTRL_TCF_ASYMM:
588 return sysfs_emit(buf, "asymm\n");
589 default:
590 return sysfs_emit(buf, "???\n");
591 }
592}
593
594static ssize_t mte_tcf_preferred_store(struct device *dev,
595 struct device_attribute *attr,
596 const char *buf, size_t count)
597{
598 u64 tcf;
599
600 if (sysfs_streq(buf, "async"))
601 tcf = MTE_CTRL_TCF_ASYNC;
602 else if (sysfs_streq(buf, "sync"))
603 tcf = MTE_CTRL_TCF_SYNC;
604 else if (cpus_have_cap(ARM64_MTE_ASYMM) && sysfs_streq(buf, "asymm"))
605 tcf = MTE_CTRL_TCF_ASYMM;
606 else
607 return -EINVAL;
608
609 device_lock(dev);
610 per_cpu(mte_tcf_preferred, dev->id) = tcf;
611 device_unlock(dev);
612
613 return count;
614}
615static DEVICE_ATTR_RW(mte_tcf_preferred);
616
617static int register_mte_tcf_preferred_sysctl(void)
618{
619 unsigned int cpu;
620
621 if (!system_supports_mte())
622 return 0;
623
624 for_each_possible_cpu(cpu) {
625 per_cpu(mte_tcf_preferred, cpu) = MTE_CTRL_TCF_ASYNC;
626 device_create_file(get_cpu_device(cpu),
627 &dev_attr_mte_tcf_preferred);
628 }
629
630 return 0;
631}
632subsys_initcall(register_mte_tcf_preferred_sysctl);
633
634/*
635 * Return 0 on success, the number of bytes not probed otherwise.
636 */
637size_t mte_probe_user_range(const char __user *uaddr, size_t size)
638{
639 const char __user *end = uaddr + size;
640 char val;
641
642 __raw_get_user(val, uaddr, efault);
643
644 uaddr = PTR_ALIGN(uaddr, MTE_GRANULE_SIZE);
645 while (uaddr < end) {
646 /*
647 * A read is sufficient for mte, the caller should have probed
648 * for the pte write permission if required.
649 */
650 __raw_get_user(val, uaddr, efault);
651 uaddr += MTE_GRANULE_SIZE;
652 }
653 (void)val;
654
655 return 0;
656
657efault:
658 return end - uaddr;
659}