projects/linux·blob master · refs

1005 lines · 25.0 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Based on arch/arm/kernel/process.c
4 *
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
8 */
9#include <linux/compat.h>
10#include <linux/efi.h>
11#include <linux/elf.h>
12#include <linux/export.h>
13#include <linux/sched.h>
14#include <linux/sched/debug.h>
15#include <linux/sched/task.h>
16#include <linux/sched/task_stack.h>
17#include <linux/kernel.h>
18#include <linux/mman.h>
19#include <linux/mm.h>
20#include <linux/nospec.h>
21#include <linux/stddef.h>
22#include <linux/sysctl.h>
23#include <linux/unistd.h>
24#include <linux/user.h>
25#include <linux/delay.h>
26#include <linux/reboot.h>
27#include <linux/interrupt.h>
28#include <linux/init.h>
29#include <linux/cpumask.h>
30#include <linux/cpu.h>
31#include <linux/elfcore.h>
32#include <linux/pm.h>
33#include <linux/tick.h>
34#include <linux/utsname.h>
35#include <linux/uaccess.h>
36#include <linux/random.h>
37#include <linux/hw_breakpoint.h>
38#include <linux/personality.h>
39#include <linux/notifier.h>
40#include <trace/events/power.h>
41#include <linux/percpu.h>
42#include <linux/thread_info.h>
43#include <linux/prctl.h>
44#include <linux/stacktrace.h>
45
46#include <asm/alternative.h>
47#include <asm/arch_timer.h>
48#include <asm/compat.h>
49#include <asm/cpufeature.h>
50#include <asm/cacheflush.h>
51#include <asm/exec.h>
52#include <asm/fpsimd.h>
53#include <asm/gcs.h>
54#include <asm/mmu_context.h>
55#include <asm/mpam.h>
56#include <asm/mte.h>
57#include <asm/processor.h>
58#include <asm/pointer_auth.h>
59#include <asm/stacktrace.h>
60#include <asm/switch_to.h>
61#include <asm/system_misc.h>
62
63#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
64#include <linux/stackprotector.h>
65unsigned long __stack_chk_guard __ro_after_init;
66EXPORT_SYMBOL(__stack_chk_guard);
67#endif
68
69/*
70 * Function pointers to optional machine specific functions
71 */
72void (*pm_power_off)(void);
73EXPORT_SYMBOL_GPL(pm_power_off);
74
75#ifdef CONFIG_HOTPLUG_CPU
76void __noreturn arch_cpu_idle_dead(void)
77{
78 cpu_die();
79}
80#endif
81
82/*
83 * Called by kexec, immediately prior to machine_kexec().
84 *
85 * This must completely disable all secondary CPUs; simply causing those CPUs
86 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
87 * kexec'd kernel to use any and all RAM as it sees fit, without having to
88 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
89 * functionality embodied in smpt_shutdown_nonboot_cpus() to achieve this.
90 */
91void machine_shutdown(void)
92{
93 smp_shutdown_nonboot_cpus(reboot_cpu);
94}
95
96/*
97 * Halting simply requires that the secondary CPUs stop performing any
98 * activity (executing tasks, handling interrupts). smp_send_stop()
99 * achieves this.
100 */
101void machine_halt(void)
102{
103 local_irq_disable();
104 smp_send_stop();
105 while (1);
106}
107
108/*
109 * Power-off simply requires that the secondary CPUs stop performing any
110 * activity (executing tasks, handling interrupts). smp_send_stop()
111 * achieves this. When the system power is turned off, it will take all CPUs
112 * with it.
113 */
114void machine_power_off(void)
115{
116 local_irq_disable();
117 smp_send_stop();
118 do_kernel_power_off();
119}
120
121/*
122 * Restart requires that the secondary CPUs stop performing any activity
123 * while the primary CPU resets the system. Systems with multiple CPUs must
124 * provide a HW restart implementation, to ensure that all CPUs reset at once.
125 * This is required so that any code running after reset on the primary CPU
126 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
127 * executing pre-reset code, and using RAM that the primary CPU's code wishes
128 * to use. Implementing such co-ordination would be essentially impossible.
129 */
130void machine_restart(char *cmd)
131{
132 /* Disable interrupts first */
133 local_irq_disable();
134 smp_send_stop();
135
136 /*
137 * UpdateCapsule() depends on the system being reset via
138 * ResetSystem().
139 */
140 if (efi_enabled(EFI_RUNTIME_SERVICES))
141 efi_reboot(reboot_mode, NULL);
142
143 /* Now call the architecture specific reboot code. */
144 do_kernel_restart(cmd);
145
146 /*
147 * Whoops - the architecture was unable to reboot.
148 */
149 printk("Reboot failed -- System halted\n");
150 while (1);
151}
152
153#define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str
154static const char *const btypes[] = {
155 bstr(NONE, "--"),
156 bstr( JC, "jc"),
157 bstr( C, "-c"),
158 bstr( J , "j-")
159};
160#undef bstr
161
162static void print_pstate(struct pt_regs *regs)
163{
164 u64 pstate = regs->pstate;
165
166 if (compat_user_mode(regs)) {
167 printk("pstate: %08llx (%c%c%c%c %c %s %s %c%c%c %cDIT %cSSBS)\n",
168 pstate,
169 pstate & PSR_AA32_N_BIT ? 'N' : 'n',
170 pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
171 pstate & PSR_AA32_C_BIT ? 'C' : 'c',
172 pstate & PSR_AA32_V_BIT ? 'V' : 'v',
173 pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
174 pstate & PSR_AA32_T_BIT ? "T32" : "A32",
175 pstate & PSR_AA32_E_BIT ? "BE" : "LE",
176 pstate & PSR_AA32_A_BIT ? 'A' : 'a',
177 pstate & PSR_AA32_I_BIT ? 'I' : 'i',
178 pstate & PSR_AA32_F_BIT ? 'F' : 'f',
179 pstate & PSR_AA32_DIT_BIT ? '+' : '-',
180 pstate & PSR_AA32_SSBS_BIT ? '+' : '-');
181 } else {
182 const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
183 PSR_BTYPE_SHIFT];
184
185 printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO %cDIT %cSSBS BTYPE=%s)\n",
186 pstate,
187 pstate & PSR_N_BIT ? 'N' : 'n',
188 pstate & PSR_Z_BIT ? 'Z' : 'z',
189 pstate & PSR_C_BIT ? 'C' : 'c',
190 pstate & PSR_V_BIT ? 'V' : 'v',
191 pstate & PSR_D_BIT ? 'D' : 'd',
192 pstate & PSR_A_BIT ? 'A' : 'a',
193 pstate & PSR_I_BIT ? 'I' : 'i',
194 pstate & PSR_F_BIT ? 'F' : 'f',
195 pstate & PSR_PAN_BIT ? '+' : '-',
196 pstate & PSR_UAO_BIT ? '+' : '-',
197 pstate & PSR_TCO_BIT ? '+' : '-',
198 pstate & PSR_DIT_BIT ? '+' : '-',
199 pstate & PSR_SSBS_BIT ? '+' : '-',
200 btype_str);
201 }
202}
203
204void __show_regs(struct pt_regs *regs)
205{
206 int i, top_reg;
207 u64 lr, sp;
208
209 if (compat_user_mode(regs)) {
210 lr = regs->compat_lr;
211 sp = regs->compat_sp;
212 top_reg = 12;
213 } else {
214 lr = regs->regs[30];
215 sp = regs->sp;
216 top_reg = 29;
217 }
218
219 show_regs_print_info(KERN_DEFAULT);
220 print_pstate(regs);
221
222 if (!user_mode(regs)) {
223 printk("pc : %pS\n", (void *)regs->pc);
224 printk("lr : %pS\n", (void *)ptrauth_strip_kernel_insn_pac(lr));
225 } else {
226 printk("pc : %016llx\n", regs->pc);
227 printk("lr : %016llx\n", lr);
228 }
229
230 printk("sp : %016llx\n", sp);
231
232 if (system_uses_irq_prio_masking())
233 printk("pmr: %08x\n", regs->pmr);
234
235 i = top_reg;
236
237 while (i >= 0) {
238 printk("x%-2d: %016llx", i, regs->regs[i]);
239
240 while (i-- % 3)
241 pr_cont(" x%-2d: %016llx", i, regs->regs[i]);
242
243 pr_cont("\n");
244 }
245}
246
247void show_regs(struct pt_regs *regs)
248{
249 __show_regs(regs);
250 dump_backtrace(regs, NULL, KERN_DEFAULT);
251}
252
253static void tls_thread_flush(void)
254{
255 write_sysreg(0, tpidr_el0);
256 if (system_supports_tpidr2())
257 write_sysreg_s(0, SYS_TPIDR2_EL0);
258
259 if (is_compat_task()) {
260 current->thread.uw.tp_value = 0;
261
262 /*
263 * We need to ensure ordering between the shadow state and the
264 * hardware state, so that we don't corrupt the hardware state
265 * with a stale shadow state during context switch.
266 */
267 barrier();
268 write_sysreg(0, tpidrro_el0);
269 }
270}
271
272static void flush_tagged_addr_state(void)
273{
274 if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
275 clear_thread_flag(TIF_TAGGED_ADDR);
276}
277
278static void flush_poe(void)
279{
280 if (!system_supports_poe())
281 return;
282
283 write_sysreg_s(POR_EL0_INIT, SYS_POR_EL0);
284}
285
286#ifdef CONFIG_ARM64_GCS
287
288static void flush_gcs(void)
289{
290 if (!system_supports_gcs())
291 return;
292
293 current->thread.gcspr_el0 = 0;
294 current->thread.gcs_base = 0;
295 current->thread.gcs_size = 0;
296 current->thread.gcs_el0_mode = 0;
297 current->thread.gcs_el0_locked = 0;
298 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1);
299 write_sysreg_s(0, SYS_GCSPR_EL0);
300}
301
302static int copy_thread_gcs(struct task_struct *p,
303 const struct kernel_clone_args *args)
304{
305 unsigned long gcs;
306
307 if (!system_supports_gcs())
308 return 0;
309
310 p->thread.gcs_base = 0;
311 p->thread.gcs_size = 0;
312
313 p->thread.gcs_el0_mode = current->thread.gcs_el0_mode;
314 p->thread.gcs_el0_locked = current->thread.gcs_el0_locked;
315
316 gcs = gcs_alloc_thread_stack(p, args);
317 if (IS_ERR_VALUE(gcs))
318 return PTR_ERR((void *)gcs);
319
320 return 0;
321}
322
323#else
324
325static void flush_gcs(void) { }
326static int copy_thread_gcs(struct task_struct *p,
327 const struct kernel_clone_args *args)
328{
329 return 0;
330}
331
332#endif
333
334void flush_thread(void)
335{
336 fpsimd_flush_thread();
337 tls_thread_flush();
338 flush_ptrace_hw_breakpoint(current);
339 flush_tagged_addr_state();
340 flush_poe();
341 flush_gcs();
342}
343
344void arch_release_task_struct(struct task_struct *tsk)
345{
346 fpsimd_release_task(tsk);
347}
348
349int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
350{
351 /*
352 * The current/src task's FPSIMD state may or may not be live, and may
353 * have been altered by ptrace after entry to the kernel. Save the
354 * effective FPSIMD state so that this will be copied into dst.
355 */
356 fpsimd_save_and_flush_current_state();
357 fpsimd_sync_from_effective_state(src);
358
359 *dst = *src;
360
361 /*
362 * Drop stale reference to src's sve_state and convert dst to
363 * non-streaming FPSIMD mode.
364 */
365 dst->thread.fp_type = FP_STATE_FPSIMD;
366 dst->thread.sve_state = NULL;
367 clear_tsk_thread_flag(dst, TIF_SVE);
368 task_smstop_sm(dst);
369
370 /*
371 * Drop stale reference to src's sme_state and ensure dst has ZA
372 * disabled.
373 *
374 * When necessary, ZA will be inherited later in copy_thread_za().
375 */
376 dst->thread.sme_state = NULL;
377 clear_tsk_thread_flag(dst, TIF_SME);
378 dst->thread.svcr &= ~SVCR_ZA_MASK;
379
380 /* clear any pending asynchronous tag fault raised by the parent */
381 clear_tsk_thread_flag(dst, TIF_MTE_ASYNC_FAULT);
382
383 return 0;
384}
385
386static int copy_thread_za(struct task_struct *dst, struct task_struct *src)
387{
388 if (!thread_za_enabled(&src->thread))
389 return 0;
390
391 dst->thread.sve_state = kzalloc(sve_state_size(src),
392 GFP_KERNEL);
393 if (!dst->thread.sve_state)
394 return -ENOMEM;
395
396 dst->thread.sme_state = kmemdup(src->thread.sme_state,
397 sme_state_size(src),
398 GFP_KERNEL);
399 if (!dst->thread.sme_state) {
400 kfree(dst->thread.sve_state);
401 dst->thread.sve_state = NULL;
402 return -ENOMEM;
403 }
404
405 set_tsk_thread_flag(dst, TIF_SME);
406 dst->thread.svcr |= SVCR_ZA_MASK;
407
408 return 0;
409}
410
411asmlinkage void ret_from_fork(void) asm("ret_from_fork");
412
413int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
414{
415 u64 clone_flags = args->flags;
416 unsigned long stack_start = args->stack;
417 unsigned long tls = args->tls;
418 struct pt_regs *childregs = task_pt_regs(p);
419 int ret;
420
421 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
422
423 /*
424 * In case p was allocated the same task_struct pointer as some
425 * other recently-exited task, make sure p is disassociated from
426 * any cpu that may have run that now-exited task recently.
427 * Otherwise we could erroneously skip reloading the FPSIMD
428 * registers for p.
429 */
430 fpsimd_flush_task_state(p);
431
432 ptrauth_thread_init_kernel(p);
433
434 if (likely(!args->fn)) {
435 *childregs = *current_pt_regs();
436 childregs->regs[0] = 0;
437
438 /*
439 * Read the current TLS pointer from tpidr_el0 as it may be
440 * out-of-sync with the saved value.
441 */
442 *task_user_tls(p) = read_sysreg(tpidr_el0);
443
444 if (system_supports_poe())
445 p->thread.por_el0 = read_sysreg_s(SYS_POR_EL0);
446
447 if (stack_start) {
448 if (is_compat_thread(task_thread_info(p)))
449 childregs->compat_sp = stack_start;
450 else
451 childregs->sp = stack_start;
452 }
453
454 /*
455 * Due to the AAPCS64 "ZA lazy saving scheme", PSTATE.ZA and
456 * TPIDR2 need to be manipulated as a pair, and either both
457 * need to be inherited or both need to be reset.
458 *
459 * Within a process, child threads must not inherit their
460 * parent's TPIDR2 value or they may clobber their parent's
461 * stack at some later point.
462 *
463 * When a process is fork()'d, the child must inherit ZA and
464 * TPIDR2 from its parent in case there was dormant ZA state.
465 *
466 * Use CLONE_VM to determine when the child will share the
467 * address space with the parent, and cannot safely inherit the
468 * state.
469 */
470 if (system_supports_sme()) {
471 if (!(clone_flags & CLONE_VM)) {
472 p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
473 ret = copy_thread_za(p, current);
474 if (ret)
475 return ret;
476 } else {
477 p->thread.tpidr2_el0 = 0;
478 WARN_ON_ONCE(p->thread.svcr & SVCR_ZA_MASK);
479 }
480 }
481
482 /*
483 * If a TLS pointer was passed to clone, use it for the new
484 * thread.
485 */
486 if (clone_flags & CLONE_SETTLS)
487 p->thread.uw.tp_value = tls;
488
489 ret = copy_thread_gcs(p, args);
490 if (ret != 0)
491 return ret;
492 } else {
493 /*
494 * A kthread has no context to ERET to, so ensure any buggy
495 * ERET is treated as an illegal exception return.
496 *
497 * When a user task is created from a kthread, childregs will
498 * be initialized by start_thread() or start_compat_thread().
499 */
500 memset(childregs, 0, sizeof(struct pt_regs));
501 childregs->pstate = PSR_MODE_EL1h | PSR_IL_BIT;
502 childregs->stackframe.type = FRAME_META_TYPE_FINAL;
503
504 p->thread.cpu_context.x19 = (unsigned long)args->fn;
505 p->thread.cpu_context.x20 = (unsigned long)args->fn_arg;
506
507 if (system_supports_poe())
508 p->thread.por_el0 = POR_EL0_INIT;
509 }
510 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
511 p->thread.cpu_context.sp = (unsigned long)childregs;
512 /*
513 * For the benefit of the unwinder, set up childregs->stackframe
514 * as the final frame for the new task.
515 */
516 p->thread.cpu_context.fp = (unsigned long)&childregs->stackframe;
517
518 ptrace_hw_copy_thread(p);
519
520 return 0;
521}
522
523void tls_preserve_current_state(void)
524{
525 *task_user_tls(current) = read_sysreg(tpidr_el0);
526 if (system_supports_tpidr2() && !is_compat_task())
527 current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
528}
529
530static void tls_thread_switch(struct task_struct *next)
531{
532 tls_preserve_current_state();
533
534 if (is_compat_thread(task_thread_info(next)))
535 write_sysreg(next->thread.uw.tp_value, tpidrro_el0);
536 else
537 write_sysreg(0, tpidrro_el0);
538
539 write_sysreg(*task_user_tls(next), tpidr_el0);
540 if (system_supports_tpidr2())
541 write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
542}
543
544/*
545 * Force SSBS state on context-switch, since it may be lost after migrating
546 * from a CPU which treats the bit as RES0 in a heterogeneous system.
547 */
548static void ssbs_thread_switch(struct task_struct *next)
549{
550 /*
551 * Nothing to do for kernel threads, but 'regs' may be junk
552 * (e.g. idle task) so check the flags and bail early.
553 */
554 if (unlikely(next->flags & PF_KTHREAD))
555 return;
556
557 /*
558 * If all CPUs implement the SSBS extension, then we just need to
559 * context-switch the PSTATE field.
560 */
561 if (alternative_has_cap_unlikely(ARM64_SSBS))
562 return;
563
564 spectre_v4_enable_task_mitigation(next);
565}
566
567/*
568 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
569 * shadow copy so that we can restore this upon entry from userspace.
570 *
571 * This is *only* for exception entry from EL0, and is not valid until we
572 * __switch_to() a user task.
573 */
574DEFINE_PER_CPU(struct task_struct *, __entry_task);
575
576static void entry_task_switch(struct task_struct *next)
577{
578 __this_cpu_write(__entry_task, next);
579}
580
581#ifdef CONFIG_ARM64_GCS
582
583void gcs_preserve_current_state(void)
584{
585 current->thread.gcspr_el0 = read_sysreg_s(SYS_GCSPR_EL0);
586}
587
588static void gcs_thread_switch(struct task_struct *next)
589{
590 if (!system_supports_gcs())
591 return;
592
593 /* GCSPR_EL0 is always readable */
594 gcs_preserve_current_state();
595 write_sysreg_s(next->thread.gcspr_el0, SYS_GCSPR_EL0);
596
597 if (current->thread.gcs_el0_mode != next->thread.gcs_el0_mode)
598 gcs_set_el0_mode(next);
599
600 /*
601 * Ensure that GCS memory effects of the 'prev' thread are
602 * ordered before other memory accesses with release semantics
603 * (or preceded by a DMB) on the current PE. In addition, any
604 * memory accesses with acquire semantics (or succeeded by a
605 * DMB) are ordered before GCS memory effects of the 'next'
606 * thread. This will ensure that the GCS memory effects are
607 * visible to other PEs in case of migration.
608 */
609 if (task_gcs_el0_enabled(current) || task_gcs_el0_enabled(next))
610 gcsb_dsync();
611}
612
613#else
614
615static void gcs_thread_switch(struct task_struct *next)
616{
617}
618
619#endif
620
621/*
622 * Handle sysreg updates for ARM erratum 1418040 which affects the 32bit view of
623 * CNTVCT, various other errata which require trapping all CNTVCT{,_EL0}
624 * accesses and prctl(PR_SET_TSC). Ensure access is disabled iff a workaround is
625 * required or PR_TSC_SIGSEGV is set.
626 */
627static void update_cntkctl_el1(struct task_struct *next)
628{
629 struct thread_info *ti = task_thread_info(next);
630
631 if (test_ti_thread_flag(ti, TIF_TSC_SIGSEGV) ||
632 has_erratum_handler(read_cntvct_el0) ||
633 (IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) &&
634 this_cpu_has_cap(ARM64_WORKAROUND_1418040) &&
635 is_compat_thread(ti)))
636 sysreg_clear_set(cntkctl_el1, ARCH_TIMER_USR_VCT_ACCESS_EN, 0);
637 else
638 sysreg_clear_set(cntkctl_el1, 0, ARCH_TIMER_USR_VCT_ACCESS_EN);
639}
640
641static void cntkctl_thread_switch(struct task_struct *prev,
642 struct task_struct *next)
643{
644 if ((read_ti_thread_flags(task_thread_info(prev)) &
645 (_TIF_32BIT | _TIF_TSC_SIGSEGV)) !=
646 (read_ti_thread_flags(task_thread_info(next)) &
647 (_TIF_32BIT | _TIF_TSC_SIGSEGV)))
648 update_cntkctl_el1(next);
649}
650
651static int do_set_tsc_mode(unsigned int val)
652{
653 bool tsc_sigsegv;
654
655 if (val == PR_TSC_SIGSEGV)
656 tsc_sigsegv = true;
657 else if (val == PR_TSC_ENABLE)
658 tsc_sigsegv = false;
659 else
660 return -EINVAL;
661
662 preempt_disable();
663 update_thread_flag(TIF_TSC_SIGSEGV, tsc_sigsegv);
664 update_cntkctl_el1(current);
665 preempt_enable();
666
667 return 0;
668}
669
670static void permission_overlay_switch(struct task_struct *next)
671{
672 if (!system_supports_poe())
673 return;
674
675 current->thread.por_el0 = read_sysreg_s(SYS_POR_EL0);
676 if (current->thread.por_el0 != next->thread.por_el0) {
677 write_sysreg_s(next->thread.por_el0, SYS_POR_EL0);
678 /*
679 * No ISB required as we can tolerate spurious Overlay faults -
680 * the fault handler will check again based on the new value
681 * of POR_EL0.
682 */
683 }
684}
685
686/*
687 * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore
688 * this function must be called with preemption disabled and the update to
689 * sctlr_user must be made in the same preemption disabled block so that
690 * __switch_to() does not see the variable update before the SCTLR_EL1 one.
691 */
692void update_sctlr_el1(u64 sctlr)
693{
694 /*
695 * EnIA must not be cleared while in the kernel as this is necessary for
696 * in-kernel PAC. It will be cleared on kernel exit if needed.
697 */
698 sysreg_clear_set(sctlr_el1, SCTLR_USER_MASK & ~SCTLR_ELx_ENIA, sctlr);
699
700 /* ISB required for the kernel uaccess routines when setting TCF0. */
701 isb();
702}
703
704static inline void debug_switch_state(void)
705{
706 if (system_uses_irq_prio_masking()) {
707 unsigned long daif_expected = 0;
708 unsigned long daif_actual = read_sysreg(daif);
709 unsigned long pmr_expected = GIC_PRIO_IRQOFF;
710 unsigned long pmr_actual = read_sysreg_s(SYS_ICC_PMR_EL1);
711
712 WARN_ONCE(daif_actual != daif_expected ||
713 pmr_actual != pmr_expected,
714 "Unexpected DAIF + PMR: 0x%lx + 0x%lx (expected 0x%lx + 0x%lx)\n",
715 daif_actual, pmr_actual,
716 daif_expected, pmr_expected);
717 } else {
718 unsigned long daif_expected = DAIF_PROCCTX_NOIRQ;
719 unsigned long daif_actual = read_sysreg(daif);
720
721 WARN_ONCE(daif_actual != daif_expected,
722 "Unexpected DAIF value: 0x%lx (expected 0x%lx)\n",
723 daif_actual, daif_expected);
724 }
725}
726
727/*
728 * Thread switching.
729 */
730__notrace_funcgraph __sched
731struct task_struct *__switch_to(struct task_struct *prev,
732 struct task_struct *next)
733{
734 struct task_struct *last;
735
736 debug_switch_state();
737
738 fpsimd_thread_switch(next);
739 tls_thread_switch(next);
740 hw_breakpoint_thread_switch(next);
741 contextidr_thread_switch(next);
742 entry_task_switch(next);
743 ssbs_thread_switch(next);
744 cntkctl_thread_switch(prev, next);
745 ptrauth_thread_switch_user(next);
746 permission_overlay_switch(next);
747 gcs_thread_switch(next);
748
749 /*
750 * Complete any pending TLB or cache maintenance on this CPU in case the
751 * thread migrates to a different CPU. This full barrier is also
752 * required by the membarrier system call. Additionally it makes any
753 * in-progress pgtable writes visible to the table walker; See
754 * emit_pte_barriers().
755 */
756 dsb(ish);
757
758 /*
759 * MTE thread switching must happen after the DSB above to ensure that
760 * any asynchronous tag check faults have been logged in the TFSR*_EL1
761 * registers.
762 */
763 mte_thread_switch(next);
764 /* avoid expensive SCTLR_EL1 accesses if no change */
765 if (prev->thread.sctlr_user != next->thread.sctlr_user)
766 update_sctlr_el1(next->thread.sctlr_user);
767
768 /*
769 * MPAM thread switch happens after the DSB to ensure prev's accesses
770 * use prev's MPAM settings.
771 */
772 mpam_thread_switch(next);
773
774 /* the actual thread switch */
775 last = cpu_switch_to(prev, next);
776
777 return last;
778}
779
780struct wchan_info {
781 unsigned long pc;
782 int count;
783};
784
785static bool get_wchan_cb(void *arg, unsigned long pc)
786{
787 struct wchan_info *wchan_info = arg;
788
789 if (!in_sched_functions(pc)) {
790 wchan_info->pc = pc;
791 return false;
792 }
793 return wchan_info->count++ < 16;
794}
795
796unsigned long __get_wchan(struct task_struct *p)
797{
798 struct wchan_info wchan_info = {
799 .pc = 0,
800 .count = 0,
801 };
802
803 if (!try_get_task_stack(p))
804 return 0;
805
806 arch_stack_walk(get_wchan_cb, &wchan_info, p, NULL);
807
808 put_task_stack(p);
809
810 return wchan_info.pc;
811}
812
813unsigned long arch_align_stack(unsigned long sp)
814{
815 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
816 sp -= get_random_u32_below(PAGE_SIZE);
817 return sp & ~0xf;
818}
819
820#ifdef CONFIG_COMPAT
821int compat_elf_check_arch(const struct elf32_hdr *hdr)
822{
823 if (!system_supports_32bit_el0())
824 return false;
825
826 if ((hdr)->e_machine != EM_ARM)
827 return false;
828
829 if (!((hdr)->e_flags & EF_ARM_EABI_MASK))
830 return false;
831
832 /*
833 * Prevent execve() of a 32-bit program from a deadline task
834 * if the restricted affinity mask would be inadmissible on an
835 * asymmetric system.
836 */
837 return !static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
838 !dl_task_check_affinity(current, system_32bit_el0_cpumask());
839}
840#endif
841
842/*
843 * Called from setup_new_exec() after (COMPAT_)SET_PERSONALITY.
844 */
845void arch_setup_new_exec(void)
846{
847 unsigned long mmflags = 0;
848
849 if (is_compat_task()) {
850 mmflags = MMCF_AARCH32;
851
852 /*
853 * Restrict the CPU affinity mask for a 32-bit task so that
854 * it contains only 32-bit-capable CPUs.
855 *
856 * From the perspective of the task, this looks similar to
857 * what would happen if the 64-bit-only CPUs were hot-unplugged
858 * at the point of execve(), although we try a bit harder to
859 * honour the cpuset hierarchy.
860 */
861 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
862 force_compatible_cpus_allowed_ptr(current);
863 } else if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) {
864 relax_compatible_cpus_allowed_ptr(current);
865 }
866
867 current->mm->context.flags = mmflags;
868 ptrauth_thread_init_user();
869 mte_thread_init_user();
870 do_set_tsc_mode(PR_TSC_ENABLE);
871
872 if (task_spec_ssb_noexec(current)) {
873 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
874 PR_SPEC_ENABLE);
875 }
876}
877
878#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
879/*
880 * Control the relaxed ABI allowing tagged user addresses into the kernel.
881 */
882static unsigned int tagged_addr_disabled;
883
884long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg)
885{
886 unsigned long valid_mask = PR_TAGGED_ADDR_ENABLE;
887 struct thread_info *ti = task_thread_info(task);
888
889 if (is_compat_thread(ti))
890 return -EINVAL;
891
892 if (system_supports_mte()) {
893 valid_mask |= PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC \
894 | PR_MTE_TAG_MASK;
895
896 if (cpus_have_cap(ARM64_MTE_STORE_ONLY))
897 valid_mask |= PR_MTE_STORE_ONLY;
898 }
899
900 if (arg & ~valid_mask)
901 return -EINVAL;
902
903 /*
904 * Do not allow the enabling of the tagged address ABI if globally
905 * disabled via sysctl abi.tagged_addr_disabled.
906 */
907 if (arg & PR_TAGGED_ADDR_ENABLE && tagged_addr_disabled)
908 return -EINVAL;
909
910 if (set_mte_ctrl(task, arg) != 0)
911 return -EINVAL;
912
913 update_ti_thread_flag(ti, TIF_TAGGED_ADDR, arg & PR_TAGGED_ADDR_ENABLE);
914
915 return 0;
916}
917
918long get_tagged_addr_ctrl(struct task_struct *task)
919{
920 long ret = 0;
921 struct thread_info *ti = task_thread_info(task);
922
923 if (is_compat_thread(ti))
924 return -EINVAL;
925
926 if (test_ti_thread_flag(ti, TIF_TAGGED_ADDR))
927 ret = PR_TAGGED_ADDR_ENABLE;
928
929 ret |= get_mte_ctrl(task);
930
931 return ret;
932}
933
934/*
935 * Global sysctl to disable the tagged user addresses support. This control
936 * only prevents the tagged address ABI enabling via prctl() and does not
937 * disable it for tasks that already opted in to the relaxed ABI.
938 */
939
940static const struct ctl_table tagged_addr_sysctl_table[] = {
941 {
942 .procname = "tagged_addr_disabled",
943 .mode = 0644,
944 .data = &tagged_addr_disabled,
945 .maxlen = sizeof(int),
946 .proc_handler = proc_dointvec_minmax,
947 .extra1 = SYSCTL_ZERO,
948 .extra2 = SYSCTL_ONE,
949 },
950};
951
952static int __init tagged_addr_init(void)
953{
954 if (!register_sysctl("abi", tagged_addr_sysctl_table))
955 return -EINVAL;
956 return 0;
957}
958
959core_initcall(tagged_addr_init);
960#endif /* CONFIG_ARM64_TAGGED_ADDR_ABI */
961
962#ifdef CONFIG_BINFMT_ELF
963int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
964 bool has_interp, bool is_interp)
965{
966 /*
967 * For dynamically linked executables the interpreter is
968 * responsible for setting PROT_BTI on everything except
969 * itself.
970 */
971 if (is_interp != has_interp)
972 return prot;
973
974 if (!(state->flags & ARM64_ELF_BTI))
975 return prot;
976
977 if (prot & PROT_EXEC)
978 prot |= PROT_BTI;
979
980 return prot;
981}
982#endif
983
984int get_tsc_mode(unsigned long adr)
985{
986 unsigned int val;
987
988 if (is_compat_task())
989 return -EINVAL;
990
991 if (test_thread_flag(TIF_TSC_SIGSEGV))
992 val = PR_TSC_SIGSEGV;
993 else
994 val = PR_TSC_ENABLE;
995
996 return put_user(val, (unsigned int __user *)adr);
997}
998
999int set_tsc_mode(unsigned int val)
1000{
1001 if (is_compat_task())
1002 return -EINVAL;
1003
1004 return do_set_tsc_mode(val);
1005}