| 1 | |
| 2 | |
| 3 | * Based on arch/arm/kernel/sys_arm.c
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| 4 | *
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| 5 | * Copyright (C) People who wrote linux/arch/i386/kernel/sys_i386.c
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| 6 | * Copyright (C) 1995, 1996 Russell King.
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| 7 | * Copyright (C) 2012 ARM Ltd.
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| 8 |
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| 9 |
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| 10 | #include <linux/compat.h>
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| 11 | #include <linux/cpufeature.h>
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| 12 | #include <linux/sched.h>
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| 13 | #include <linux/sched/signal.h>
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| 14 | #include <linux/slab.h>
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| 15 | #include <linux/syscalls.h>
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| 16 | #include <linux/uaccess.h>
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| 17 |
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| 18 | #include <asm/cacheflush.h>
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| 19 | #include <asm/system_misc.h>
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| 20 | #include <asm/tlbflush.h>
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| 21 | #include <asm/unistd.h>
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| 22 |
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| 23 | static long
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| 24 | __do_compat_cache_op(unsigned long start, unsigned long end)
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| 25 | {
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| 26 | long ret;
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| 27 |
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| 28 | do {
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| 29 | unsigned long chunk = min(PAGE_SIZE, end - start);
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| 30 |
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| 31 | if (fatal_signal_pending(current))
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| 32 | return 0;
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| 33 |
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| 34 | if (cpus_have_final_cap(ARM64_WORKAROUND_1542419)) {
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| 35 | |
| 36 | * The workaround requires an inner-shareable tlbi.
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| 37 | * We pick the reserved-ASID to minimise the impact.
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| 38 |
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| 39 | __tlbi(aside1is, 0UL);
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| 40 | __tlbi_sync_s1ish(current->mm);
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| 41 | }
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| 42 |
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| 43 | ret = caches_clean_inval_user_pou(start, start + chunk);
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| 44 | if (ret)
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| 45 | return ret;
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| 46 |
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| 47 | cond_resched();
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| 48 | start += chunk;
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| 49 | } while (start < end);
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| 50 |
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| 51 | return 0;
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| 52 | }
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| 53 |
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| 54 | static inline long
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| 55 | do_compat_cache_op(unsigned long start, unsigned long end, int flags)
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| 56 | {
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| 57 | if (end < start || flags)
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| 58 | return -EINVAL;
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| 59 |
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| 60 | if (!access_ok((const void __user *)start, end - start))
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| 61 | return -EFAULT;
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| 62 |
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| 63 | return __do_compat_cache_op(start, end);
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| 64 | }
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| 65 | |
| 66 | * Handle all unrecognised system calls.
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| 67 |
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| 68 | long compat_arm_syscall(struct pt_regs *regs, int scno)
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| 69 | {
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| 70 | unsigned long addr;
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| 71 |
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| 72 | switch (scno) {
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| 73 | |
| 74 | * Flush a region from virtual address 'r0' to virtual address 'r1'
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| 75 | * _exclusive_. There is no alignment requirement on either address;
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| 76 | * user space does not need to know the hardware cache layout.
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| 77 | *
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| 78 | * r2 contains flags. It should ALWAYS be passed as ZERO until it
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| 79 | * is defined to be something else. For now we ignore it, but may
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| 80 | * the fires of hell burn in your belly if you break this rule. ;)
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| 81 | *
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| 82 | * (at a later date, we may want to allow this call to not flush
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| 83 | * various aspects of the cache. Passing '0' will guarantee that
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| 84 | * everything necessary gets flushed to maintain consistency in
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| 85 | * the specified region).
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| 86 |
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| 87 | case __ARM_NR_compat_cacheflush:
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| 88 | return do_compat_cache_op(regs->regs[0], regs->regs[1], regs->regs[2]);
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| 89 |
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| 90 | case __ARM_NR_compat_set_tls:
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| 91 | current->thread.uw.tp_value = regs->regs[0];
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| 92 |
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| 93 | |
| 94 | * Protect against register corruption from context switch.
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| 95 | * See comment in tls_thread_flush.
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| 96 |
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| 97 | barrier();
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| 98 | write_sysreg(regs->regs[0], tpidrro_el0);
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| 99 | return 0;
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| 100 |
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| 101 | default:
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| 102 | |
| 103 | * Calls 0xf0xxx..0xf07ff are defined to return -ENOSYS
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| 104 | * if not implemented, rather than raising SIGILL. This
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| 105 | * way the calling program can gracefully determine whether
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| 106 | * a feature is supported.
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| 107 |
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| 108 | if (scno < __ARM_NR_COMPAT_END)
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| 109 | return -ENOSYS;
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| 110 | break;
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| 111 | }
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| 112 |
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| 113 | addr = instruction_pointer(regs) - (compat_thumb_mode(regs) ? 2 : 4);
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| 114 |
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| 115 | arm64_notify_die("Oops - bad compat syscall(2)", regs,
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| 116 | SIGILL, ILL_ILLTRP, addr, 0);
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| 117 | return 0;
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| 118 | }
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