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| 2 | |
| 3 | * Cache operations for the cache instruction.
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| 4 | *
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| 5 | * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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| 6 |
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| 7 | #ifndef __ASM_CACHEOPS_H
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| 8 | #define __ASM_CACHEOPS_H
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| 9 |
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| 10 | |
| 11 | * Most cache ops are split into a 3 bit field identifying the cache, and a 2
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| 12 | * bit field identifying the cache operation.
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| 13 |
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| 14 | #define CacheOp_Cache 0x07
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| 15 | #define CacheOp_Op 0x18
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| 16 |
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| 17 | #define Cache_LEAF0 0x00
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| 18 | #define Cache_LEAF1 0x01
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| 19 | #define Cache_LEAF2 0x02
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| 20 | #define Cache_LEAF3 0x03
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| 21 | #define Cache_LEAF4 0x04
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| 22 | #define Cache_LEAF5 0x05
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| 23 |
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| 24 | #define Index_Invalidate 0x08
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| 25 | #define Index_Writeback_Inv 0x08
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| 26 | #define Hit_Invalidate 0x10
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| 27 | #define Hit_Writeback_Inv 0x10
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| 28 | #define CacheOp_User_Defined 0x18
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| 29 |
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| 30 | #define Index_Writeback_Inv_LEAF0 (Cache_LEAF0 | Index_Writeback_Inv)
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| 31 | #define Index_Writeback_Inv_LEAF1 (Cache_LEAF1 | Index_Writeback_Inv)
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| 32 | #define Index_Writeback_Inv_LEAF2 (Cache_LEAF2 | Index_Writeback_Inv)
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| 33 | #define Index_Writeback_Inv_LEAF3 (Cache_LEAF3 | Index_Writeback_Inv)
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| 34 | #define Index_Writeback_Inv_LEAF4 (Cache_LEAF4 | Index_Writeback_Inv)
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| 35 | #define Index_Writeback_Inv_LEAF5 (Cache_LEAF5 | Index_Writeback_Inv)
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| 36 | #define Hit_Writeback_Inv_LEAF0 (Cache_LEAF0 | Hit_Writeback_Inv)
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| 37 | #define Hit_Writeback_Inv_LEAF1 (Cache_LEAF1 | Hit_Writeback_Inv)
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| 38 | #define Hit_Writeback_Inv_LEAF2 (Cache_LEAF2 | Hit_Writeback_Inv)
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| 39 | #define Hit_Writeback_Inv_LEAF3 (Cache_LEAF3 | Hit_Writeback_Inv)
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| 40 | #define Hit_Writeback_Inv_LEAF4 (Cache_LEAF4 | Hit_Writeback_Inv)
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| 41 | #define Hit_Writeback_Inv_LEAF5 (Cache_LEAF5 | Hit_Writeback_Inv)
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| 42 |
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| 43 | #endif
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