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| 2 | * Copyright (C) 2004, 2007 Maciej W. Rozycki
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| 3 | *
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| 4 | * This file is subject to the terms and conditions of the GNU General Public
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| 5 | * License. See the file "COPYING" in the main directory of this archive
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| 6 | * for more details.
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| 7 |
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| 8 | #ifndef _ASM_COMPILER_H
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| 9 | #define _ASM_COMPILER_H
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| 10 |
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| 11 | |
| 12 | * With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the
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| 13 | * compiler that a particular code path will never be hit. This allows it to be
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| 14 | * optimised out of the generated binary.
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| 15 | *
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| 16 | * Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug
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| 17 | * that can lead to instructions from beyond an unreachable statement being
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| 18 | * incorrectly reordered into earlier delay slots if the unreachable statement
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| 19 | * is the only content of a case in a switch statement. This can lead to
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| 20 | * seemingly random behaviour, such as invalid memory accesses from incorrectly
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| 21 | * reordered loads or stores. See this potential GCC fix for details:
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| 22 | *
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| 23 | * https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html
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| 24 | *
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| 25 | * It is unclear whether GCC 8 onwards suffer from the same issue - nothing
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| 26 | * relevant is mentioned in GCC 8 release notes and nothing obviously relevant
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| 27 | * stands out in GCC commit logs, but these newer GCC versions generate very
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| 28 | * different code for the testcase which doesn't exhibit the bug.
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| 29 | *
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| 30 | * GCC also handles stack allocation suboptimally when calling noreturn
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| 31 | * functions or calling __builtin_unreachable():
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| 32 | *
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| 33 | * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
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| 34 | *
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| 35 | * We work around both of these issues by placing a volatile asm statement,
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| 36 | * which GCC is prevented from reordering past, prior to __builtin_unreachable
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| 37 | * calls.
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| 38 | *
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| 39 | * The .insn statement is required to ensure that any branches to the
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| 40 | * statement, which sadly must be kept due to the asm statement, are known to
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| 41 | * be branches to code and satisfy linker requirements for microMIPS kernels.
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| 42 |
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| 43 | #undef barrier_before_unreachable
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| 44 | #define barrier_before_unreachable() asm volatile(".insn")
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| 45 |
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| 46 | #define GCC_OFF_SMALL_ASM() "ZC"
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| 47 |
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| 48 | #ifdef CONFIG_CPU_MIPSR6
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| 49 | #define MIPS_ISA_LEVEL "mips64r6"
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| 50 | #define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
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| 51 | #define MIPS_ISA_LEVEL_RAW mips64r6
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| 52 | #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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| 53 | #elif defined(CONFIG_CPU_MIPSR5)
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| 54 | #define MIPS_ISA_LEVEL "mips64r5"
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| 55 | #define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
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| 56 | #define MIPS_ISA_LEVEL_RAW mips64r5
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| 57 | #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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| 58 | #else
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| 59 |
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| 60 | #define MIPS_ISA_LEVEL "mips64r2"
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| 61 | #define MIPS_ISA_ARCH_LEVEL "arch=r4000"
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| 62 | #define MIPS_ISA_LEVEL_RAW mips64r2
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| 63 | #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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| 64 | #endif
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| 65 |
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| 66 | #endif
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