| 1 |
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| 2 | |
| 3 | * Copyright (C) 2014 Imagination Technologies Ltd
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| 4 | *
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| 5 | * PM helper macros for CPU power off (e.g. Suspend-to-RAM).
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| 6 |
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| 7 |
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| 8 | #ifndef __ASM_PM_H
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| 9 | #define __ASM_PM_H
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| 10 |
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| 11 | #ifdef __ASSEMBLER__
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| 12 |
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| 13 | #include <asm/asm-offsets.h>
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| 14 | #include <asm/asm.h>
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| 15 | #include <asm/mipsregs.h>
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| 16 | #include <asm/regdef.h>
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| 17 |
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| 18 |
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| 19 | .macro SUSPEND_SAVE_REGS
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| 20 | PTR_SUBU sp, PT_SIZE
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| 21 |
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| 22 | LONG_S $16, PT_R16(sp)
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| 23 | LONG_S $17, PT_R17(sp)
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| 24 | LONG_S $18, PT_R18(sp)
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| 25 | LONG_S $19, PT_R19(sp)
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| 26 | LONG_S $20, PT_R20(sp)
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| 27 | LONG_S $21, PT_R21(sp)
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| 28 | LONG_S $22, PT_R22(sp)
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| 29 | LONG_S $23, PT_R23(sp)
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| 30 | LONG_S $28, PT_R28(sp)
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| 31 | LONG_S $30, PT_R30(sp)
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| 32 | LONG_S $31, PT_R31(sp)
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| 33 |
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| 34 | mfc0 k0, CP0_STATUS
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| 35 | LONG_S k0, PT_STATUS(sp)
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| 36 | .endm
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| 37 |
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| 38 |
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| 39 | .macro RESUME_RESTORE_REGS_RETURN
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| 40 | .set push
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| 41 | .set noreorder
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| 42 |
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| 43 | LONG_L k0, PT_STATUS(sp)
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| 44 | mtc0 k0, CP0_STATUS
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| 45 |
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| 46 | LONG_L $16, PT_R16(sp)
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| 47 | LONG_L $17, PT_R17(sp)
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| 48 | LONG_L $18, PT_R18(sp)
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| 49 | LONG_L $19, PT_R19(sp)
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| 50 | LONG_L $20, PT_R20(sp)
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| 51 | LONG_L $21, PT_R21(sp)
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| 52 | LONG_L $22, PT_R22(sp)
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| 53 | LONG_L $23, PT_R23(sp)
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| 54 | LONG_L $28, PT_R28(sp)
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| 55 | LONG_L $30, PT_R30(sp)
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| 56 | LONG_L $31, PT_R31(sp)
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| 57 |
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| 58 | jr ra
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| 59 | PTR_ADDIU sp, PT_SIZE
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| 60 | .set pop
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| 61 | .endm
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| 62 |
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| 63 |
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| 64 | .macro LA_STATIC_SUSPEND
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| 65 | PTR_LA t1, mips_static_suspend_state
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| 66 | .endm
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| 67 |
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| 68 |
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| 69 | .macro SUSPEND_SAVE_STATIC
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| 70 | #ifdef CONFIG_EVA
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| 71 | |
| 72 | * Segment configuration is saved in global data where it can be easily
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| 73 | * reloaded without depending on the segment configuration.
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| 74 |
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| 75 | mfc0 k0, CP0_SEGCTL0
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| 76 | LONG_S k0, SSS_SEGCTL0(t1)
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| 77 | mfc0 k0, CP0_SEGCTL1
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| 78 | LONG_S k0, SSS_SEGCTL1(t1)
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| 79 | mfc0 k0, CP0_SEGCTL2
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| 80 | LONG_S k0, SSS_SEGCTL2(t1)
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| 81 | #endif
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| 82 |
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| 83 | LONG_S sp, SSS_SP(t1)
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| 84 | .endm
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| 85 |
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| 86 |
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| 87 | .macro RESUME_RESTORE_STATIC
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| 88 | #ifdef CONFIG_EVA
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| 89 | |
| 90 | * Segment configuration must be restored prior to any access to
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| 91 | * allocated memory, as it may reside outside of the legacy kernel
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| 92 | * segments.
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| 93 |
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| 94 | LONG_L k0, SSS_SEGCTL0(t1)
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| 95 | mtc0 k0, CP0_SEGCTL0
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| 96 | LONG_L k0, SSS_SEGCTL1(t1)
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| 97 | mtc0 k0, CP0_SEGCTL1
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| 98 | LONG_L k0, SSS_SEGCTL2(t1)
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| 99 | mtc0 k0, CP0_SEGCTL2
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| 100 | tlbw_use_hazard
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| 101 | #endif
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| 102 |
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| 103 | LONG_L sp, SSS_SP(t1)
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| 104 | .endm
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| 105 |
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| 106 |
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| 107 | .macro SUSPEND_CACHE_FLUSH
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| 108 | .extern __flush_cache_all
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| 109 | .set push
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| 110 | .set noreorder
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| 111 | PTR_LA t1, __flush_cache_all
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| 112 | LONG_L t0, 0(t1)
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| 113 | jalr t0
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| 114 | nop
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| 115 | .set pop
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| 116 | .endm
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| 117 |
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| 118 |
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| 119 | .macro SUSPEND_SAVE
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| 120 | SUSPEND_SAVE_REGS
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| 121 | LA_STATIC_SUSPEND
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| 122 | SUSPEND_SAVE_STATIC
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| 123 | SUSPEND_CACHE_FLUSH
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| 124 | .endm
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| 125 |
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| 126 |
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| 127 | .macro RESUME_RESTORE_RETURN
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| 128 | LA_STATIC_SUSPEND
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| 129 | RESUME_RESTORE_STATIC
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| 130 | RESUME_RESTORE_REGS_RETURN
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| 131 | .endm
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| 132 |
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| 133 | #else
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| 134 |
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| 135 | |
| 136 | * struct mips_static_suspend_state - Core saved CPU state across S2R.
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| 137 | * @segctl: CP0 Segment control registers.
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| 138 | * @sp: Stack frame where GP register context is saved.
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| 139 | *
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| 140 | * This structure contains minimal CPU state that must be saved in static kernel
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| 141 | * data in order to be able to restore the rest of the state. This includes
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| 142 | * segmentation configuration in the case of EVA being enabled, as they must be
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| 143 | * restored prior to any kmalloc'd memory being referenced (even the stack
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| 144 | * pointer).
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| 145 |
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| 146 | struct mips_static_suspend_state {
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| 147 | #ifdef CONFIG_EVA
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| 148 | unsigned long segctl[3];
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| 149 | #endif
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| 150 | unsigned long sp;
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| 151 | };
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| 152 |
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| 153 | #endif
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| 154 |
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| 155 | #endif
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