projects/linux·blob master · refs

154 lines · 3.4 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Ralink RT2880 timer
4 * Author: John Crispin
5 *
6 * Copyright (C) 2013 John Crispin <[email protected]>
7*/
8
9#include <linux/bits.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/timer.h>
17#include <linux/types.h>
18
19#include <asm/mach-ralink/ralink_regs.h>
20
21#define TIMER_REG_TMRSTAT 0x00
22#define TIMER_REG_TMR0LOAD 0x10
23#define TIMER_REG_TMR0CTL 0x18
24
25#define TMRSTAT_TMR0INT BIT(0)
26
27#define TMR0CTL_ENABLE BIT(7)
28#define TMR0CTL_MODE_PERIODIC BIT(4)
29#define TMR0CTL_PRESCALER 1
30#define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
31#define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
32
33struct rt_timer {
34 struct device *dev;
35 void __iomem *membase;
36 int irq;
37 unsigned long timer_freq;
38 unsigned long timer_div;
39};
40
41static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
42{
43 __raw_writel(val, rt->membase + reg);
44}
45
46static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
47{
48 return __raw_readl(rt->membase + reg);
49}
50
51static irqreturn_t rt_timer_irq(int irq, void *_rt)
52{
53 struct rt_timer *rt = (struct rt_timer *) _rt;
54
55 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
56 rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
57
58 return IRQ_HANDLED;
59}
60
61
62static int rt_timer_request(struct rt_timer *rt)
63{
64 int err = request_irq(rt->irq, rt_timer_irq, 0,
65 dev_name(rt->dev), rt);
66 if (err) {
67 dev_err(rt->dev, "failed to request irq\n");
68 } else {
69 u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
70 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
71 }
72 return err;
73}
74
75static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
76{
77 if (rt->timer_freq < divisor)
78 rt->timer_div = rt->timer_freq;
79 else
80 rt->timer_div = divisor;
81
82 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
83
84 return 0;
85}
86
87static int rt_timer_enable(struct rt_timer *rt)
88{
89 u32 t;
90
91 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
92
93 t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
94 t |= TMR0CTL_ENABLE;
95 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
96
97 return 0;
98}
99
100static int rt_timer_probe(struct platform_device *pdev)
101{
102 struct rt_timer *rt;
103 struct clk *clk;
104
105 rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
106 if (!rt) {
107 dev_err(&pdev->dev, "failed to allocate memory\n");
108 return -ENOMEM;
109 }
110
111 rt->irq = platform_get_irq(pdev, 0);
112 if (rt->irq < 0)
113 return rt->irq;
114
115 rt->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
116 if (IS_ERR(rt->membase))
117 return PTR_ERR(rt->membase);
118
119 clk = devm_clk_get(&pdev->dev, NULL);
120 if (IS_ERR(clk)) {
121 dev_err(&pdev->dev, "failed get clock rate\n");
122 return PTR_ERR(clk);
123 }
124
125 rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
126 if (!rt->timer_freq)
127 return -EINVAL;
128
129 rt->dev = &pdev->dev;
130 platform_set_drvdata(pdev, rt);
131
132 rt_timer_request(rt);
133 rt_timer_config(rt, 2);
134 rt_timer_enable(rt);
135
136 dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq);
137
138 return 0;
139}
140
141static const struct of_device_id rt_timer_match[] = {
142 { .compatible = "ralink,rt2880-timer" },
143 {},
144};
145
146static struct platform_driver rt_timer_driver = {
147 .probe = rt_timer_probe,
148 .driver = {
149 .name = "rt-timer",
150 .of_match_table = rt_timer_match,
151 .suppress_bind_attrs = true,
152 },
153};
154builtin_platform_driver(rt_timer_driver);