| 1 |
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| 2 | |
| 3 | * OpenRISC Linux
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| 4 | *
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| 5 | * Linux architectural port borrowing liberally from similar works of
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| 6 | * others. All original copyrights apply as per the original source
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| 7 | * declaration.
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| 8 | *
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| 9 | * OpenRISC implementation:
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| 10 | * Copyright (C) Jan Henrik Weinstock <[email protected]>
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| 11 | * et al.
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| 12 |
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| 13 |
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| 14 | #ifndef __ASM_CACHEFLUSH_H
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| 15 | #define __ASM_CACHEFLUSH_H
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| 16 |
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| 17 | #include <linux/mm.h>
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| 18 |
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| 19 | |
| 20 | * Helper function for flushing or invalidating entire pages from data
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| 21 | * and instruction caches. SMP needs a little extra work, since we need
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| 22 | * to flush the pages on all cpus.
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| 23 |
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| 24 | extern void local_dcache_page_flush(struct page *page);
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| 25 | extern void local_icache_page_inv(struct page *page);
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| 26 | extern void local_dcache_range_flush(unsigned long start, unsigned long end);
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| 27 | extern void local_dcache_range_inv(unsigned long start, unsigned long end);
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| 28 | extern void local_icache_range_inv(unsigned long start, unsigned long end);
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| 29 | extern void local_icache_all_inv(void);
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| 30 |
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| 31 | |
| 32 | * Data cache flushing always happen on the local cpu. Instruction cache
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| 33 | * invalidations need to be broadcasted to all other cpu in the system in
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| 34 | * case of SMP configurations.
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| 35 |
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| 36 | #ifndef CONFIG_SMP
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| 37 | #define dcache_page_flush(page) local_dcache_page_flush(page)
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| 38 | #define icache_page_inv(page) local_icache_page_inv(page)
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| 39 | #define icache_all_inv() local_icache_all_inv()
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| 40 | #else
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| 41 | #define dcache_page_flush(page) local_dcache_page_flush(page)
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| 42 | #define icache_page_inv(page) smp_icache_page_inv(page)
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| 43 | #define icache_all_inv() smp_icache_all_inv()
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| 44 | extern void smp_icache_page_inv(struct page *page);
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| 45 | extern void smp_icache_all_inv(void);
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| 46 | #endif
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| 47 |
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| 48 | |
| 49 | * Even if the actual block size is larger than L1_CACHE_BYTES, paddr
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| 50 | * can be incremented by L1_CACHE_BYTES. When paddr is written to the
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| 51 | * invalidate register, the entire cache line encompassing this address
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| 52 | * is invalidated. Each subsequent reference to the same cache line will
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| 53 | * not affect the invalidation process.
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| 54 |
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| 55 | #define local_dcache_block_flush(addr) \
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| 56 | local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)
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| 57 | #define local_dcache_block_inv(addr) \
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| 58 | local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)
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| 59 | #define local_icache_block_inv(addr) \
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| 60 | local_icache_range_inv(addr, addr + L1_CACHE_BYTES)
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| 61 |
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| 62 | |
| 63 | * Synchronizes caches. Whenever a cpu writes executable code to memory, this
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| 64 | * should be called to make sure the processor sees the newly written code.
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| 65 |
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| 66 | static inline void sync_icache_dcache(struct page *page)
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| 67 | {
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| 68 | if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
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| 69 | dcache_page_flush(page);
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| 70 | icache_page_inv(page);
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| 71 | }
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| 72 |
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| 73 | |
| 74 | * Pages with this bit set need not be flushed/invalidated, since
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| 75 | * they have not changed since last flush. New pages start with
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| 76 | * PG_arch_1 not set and are therefore dirty by default.
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| 77 |
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| 78 | #define PG_dc_clean PG_arch_1
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| 79 |
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| 80 | static inline void flush_dcache_folio(struct folio *folio)
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| 81 | {
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| 82 | clear_bit(PG_dc_clean, &folio->flags.f);
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| 83 | }
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| 84 | #define flush_dcache_folio flush_dcache_folio
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| 85 |
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| 86 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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| 87 | static inline void flush_dcache_page(struct page *page)
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| 88 | {
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| 89 | flush_dcache_folio(page_folio(page));
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| 90 | }
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| 91 |
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| 92 | #define flush_icache_user_page(vma, page, addr, len) \
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| 93 | do { \
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| 94 | if (vma->vm_flags & VM_EXEC) \
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| 95 | sync_icache_dcache(page); \
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| 96 | } while (0)
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| 97 |
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| 98 | #include <asm-generic/cacheflush.h>
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| 99 |
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| 100 | #endif
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