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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Unaligned memory access handler
4 *
5 * Copyright (C) 2001 Randolph Chung <[email protected]>
6 * Copyright (C) 2022 Helge Deller <[email protected]>
7 * Significantly tweaked by LaMont Jones <[email protected]>
8 */
9
10#include <linux/sched/signal.h>
11#include <linux/signal.h>
12#include <linux/ratelimit.h>
13#include <linux/uaccess.h>
14#include <linux/sysctl.h>
15#include <linux/unaligned.h>
16#include <linux/perf_event.h>
17#include <asm/hardirq.h>
18#include <asm/traps.h>
19#include "unaligned.h"
20
21/* #define DEBUG_UNALIGNED 1 */
22
23#ifdef DEBUG_UNALIGNED
24#define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
25#else
26#define DPRINTF(fmt, args...)
27#endif
28
29#define RFMT "0x%08lx"
30
31/* 1111 1100 0000 0000 0001 0011 1100 0000 */
32#define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
33#define OPCODE2(a,b) ((a)<<26|(b)<<1)
34#define OPCODE3(a,b) ((a)<<26|(b)<<2)
35#define OPCODE4(a) ((a)<<26)
36#define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
37#define OPCODE2_MASK OPCODE2(0x3f,1)
38#define OPCODE3_MASK OPCODE3(0x3f,1)
39#define OPCODE4_MASK OPCODE4(0x3f)
40
41/* skip LDB - never unaligned (index) */
42#define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
43#define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
44#define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
45#define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
46#define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
47#define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
48#define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
49/* skip LDB - never unaligned (short) */
50#define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
51#define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
52#define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
53#define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
54#define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
55#define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
56#define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
57/* skip STB - never unaligned */
58#define OPCODE_STH OPCODE1(0x03,1,0x9)
59#define OPCODE_STW OPCODE1(0x03,1,0xa)
60#define OPCODE_STD OPCODE1(0x03,1,0xb)
61/* skip STBY - never unaligned */
62/* skip STDBY - never unaligned */
63#define OPCODE_STWA OPCODE1(0x03,1,0xe)
64#define OPCODE_STDA OPCODE1(0x03,1,0xf)
65
66#define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
67#define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
68#define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
69#define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
70#define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
71#define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
72#define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
73#define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
74#define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
75#define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
76#define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
77#define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
78
79#define OPCODE_LDD_L OPCODE2(0x14,0)
80#define OPCODE_FLDD_L OPCODE2(0x14,1)
81#define OPCODE_STD_L OPCODE2(0x1c,0)
82#define OPCODE_FSTD_L OPCODE2(0x1c,1)
83
84#define OPCODE_LDW_M OPCODE3(0x17,1)
85#define OPCODE_FLDW_L OPCODE3(0x17,0)
86#define OPCODE_FSTW_L OPCODE3(0x1f,0)
87#define OPCODE_STW_M OPCODE3(0x1f,1)
88
89#define OPCODE_LDH_L OPCODE4(0x11)
90#define OPCODE_LDW_L OPCODE4(0x12)
91#define OPCODE_LDWM OPCODE4(0x13)
92#define OPCODE_STH_L OPCODE4(0x19)
93#define OPCODE_STW_L OPCODE4(0x1A)
94#define OPCODE_STWM OPCODE4(0x1B)
95
96#define MAJOR_OP(i) (((i)>>26)&0x3f)
97#define R1(i) (((i)>>21)&0x1f)
98#define R2(i) (((i)>>16)&0x1f)
99#define R3(i) ((i)&0x1f)
100#define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
101#define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
102#define IM5_2(i) IM((i)>>16,5)
103#define IM5_3(i) IM((i),5)
104#define IM14(i) IM((i),14)
105
106#define ERR_NOTHANDLED -1
107
108int unaligned_enabled __read_mostly = 1;
109int no_unaligned_warning __read_mostly;
110
111static int emulate_ldh(struct pt_regs *regs, int toreg)
112{
113 unsigned long saddr = regs->ior;
114 unsigned long val = 0, temp1;
115 ASM_EXCEPTIONTABLE_VAR(ret);
116
117 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
118 regs->isr, regs->ior, toreg);
119
120 __asm__ __volatile__ (
121" mtsp %4, %%sr1\n"
122"1: ldbs 0(%%sr1,%3), %2\n"
123"2: ldbs 1(%%sr1,%3), %0\n"
124" depw %2, 23, 24, %0\n"
125"3: \n"
126 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
127 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
128 : "+r" (val), "+r" (ret), "=&r" (temp1)
129 : "r" (saddr), "r" (regs->isr) );
130
131 DPRINTF("val = " RFMT "\n", val);
132
133 if (toreg)
134 regs->gr[toreg] = val;
135
136 return ret;
137}
138
139static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
140{
141 unsigned long saddr = regs->ior;
142 unsigned long val = 0, temp1, temp2;
143 ASM_EXCEPTIONTABLE_VAR(ret);
144
145 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
146 regs->isr, regs->ior, toreg);
147
148 __asm__ __volatile__ (
149" zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */
150" mtsp %5, %%sr1\n"
151" depw %%r0,31,2,%4\n"
152"1: ldw 0(%%sr1,%4),%0\n"
153"2: ldw 4(%%sr1,%4),%3\n"
154" subi 32,%2,%2\n"
155" mtctl %2,11\n"
156" vshd %0,%3,%0\n"
157"3: \n"
158 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
159 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
160 : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
161 : "r" (saddr), "r" (regs->isr) );
162
163 DPRINTF("val = " RFMT "\n", val);
164
165 if (flop)
166 ((__u32*)(regs->fr))[toreg] = val;
167 else if (toreg)
168 regs->gr[toreg] = val;
169
170 return ret;
171}
172static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
173{
174 unsigned long saddr = regs->ior;
175 unsigned long shift, temp1;
176 __u64 val = 0;
177 ASM_EXCEPTIONTABLE_VAR(ret);
178
179 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
180 regs->isr, regs->ior, toreg);
181
182 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
183 return ERR_NOTHANDLED;
184
185#ifdef CONFIG_64BIT
186 __asm__ __volatile__ (
187" depd,z %2,60,3,%3\n" /* shift=(ofs&7)*8 */
188" mtsp %5, %%sr1\n"
189" depd %%r0,63,3,%2\n"
190"1: ldd 0(%%sr1,%2),%0\n"
191"2: ldd 8(%%sr1,%2),%4\n"
192" subi 64,%3,%3\n"
193" mtsar %3\n"
194" shrpd %0,%4,%%sar,%0\n"
195"3: \n"
196 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
197 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
198 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
199 : "r" (regs->isr) );
200#else
201 __asm__ __volatile__ (
202" zdep %2,29,2,%3\n" /* shift=(ofs&3)*8 */
203" mtsp %5, %%sr1\n"
204" dep %%r0,31,2,%2\n"
205"1: ldw 0(%%sr1,%2),%0\n"
206"2: ldw 4(%%sr1,%2),%R0\n"
207"3: ldw 8(%%sr1,%2),%4\n"
208" subi 32,%3,%3\n"
209" mtsar %3\n"
210" vshd %0,%R0,%0\n"
211" vshd %R0,%4,%R0\n"
212"4: \n"
213 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
214 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
215 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
216 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
217 : "r" (regs->isr) );
218#endif
219
220 DPRINTF("val = 0x%llx\n", val);
221
222 if (flop)
223 regs->fr[toreg] = val;
224 else if (toreg)
225 regs->gr[toreg] = val;
226
227 return ret;
228}
229
230static int emulate_sth(struct pt_regs *regs, int frreg)
231{
232 unsigned long val = regs->gr[frreg], temp1;
233 ASM_EXCEPTIONTABLE_VAR(ret);
234
235 if (!frreg)
236 val = 0;
237
238 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
239 val, regs->isr, regs->ior);
240
241 __asm__ __volatile__ (
242" mtsp %4, %%sr1\n"
243" extrw,u %2, 23, 8, %1\n"
244"1: stb %1, 0(%%sr1, %3)\n"
245"2: stb %2, 1(%%sr1, %3)\n"
246"3: \n"
247 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
248 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
249 : "+r" (ret), "=&r" (temp1)
250 : "r" (val), "r" (regs->ior), "r" (regs->isr) );
251
252 return ret;
253}
254
255static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
256{
257 unsigned long val;
258 ASM_EXCEPTIONTABLE_VAR(ret);
259
260 if (flop)
261 val = ((__u32*)(regs->fr))[frreg];
262 else if (frreg)
263 val = regs->gr[frreg];
264 else
265 val = 0;
266
267 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
268 val, regs->isr, regs->ior);
269
270
271 __asm__ __volatile__ (
272" mtsp %3, %%sr1\n"
273" zdep %2, 28, 2, %%r19\n"
274" dep %%r0, 31, 2, %2\n"
275" mtsar %%r19\n"
276" depwi,z -2, %%sar, 32, %%r19\n"
277"1: ldw 0(%%sr1,%2),%%r20\n"
278"2: ldw 4(%%sr1,%2),%%r21\n"
279" vshd %%r0, %1, %%r22\n"
280" vshd %1, %%r0, %%r1\n"
281" and %%r20, %%r19, %%r20\n"
282" andcm %%r21, %%r19, %%r21\n"
283" or %%r22, %%r20, %%r20\n"
284" or %%r1, %%r21, %%r21\n"
285" stw %%r20,0(%%sr1,%2)\n"
286" stw %%r21,4(%%sr1,%2)\n"
287"3: \n"
288 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
289 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
290 : "+r" (ret)
291 : "r" (val), "r" (regs->ior), "r" (regs->isr)
292 : "r19", "r20", "r21", "r22", "r1" );
293
294 return ret;
295}
296static int emulate_std(struct pt_regs *regs, int frreg, int flop)
297{
298 __u64 val;
299 ASM_EXCEPTIONTABLE_VAR(ret);
300
301 if (flop)
302 val = regs->fr[frreg];
303 else if (frreg)
304 val = regs->gr[frreg];
305 else
306 val = 0;
307
308 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
309 val, regs->isr, regs->ior);
310
311 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
312 return ERR_NOTHANDLED;
313
314#ifdef CONFIG_64BIT
315 __asm__ __volatile__ (
316" mtsp %3, %%sr1\n"
317" depd,z %2, 60, 3, %%r19\n"
318" depd %%r0, 63, 3, %2\n"
319" mtsar %%r19\n"
320" depdi,z -2, %%sar, 64, %%r19\n"
321"1: ldd 0(%%sr1,%2),%%r20\n"
322"2: ldd 8(%%sr1,%2),%%r21\n"
323" shrpd %%r0, %1, %%sar, %%r22\n"
324" shrpd %1, %%r0, %%sar, %%r1\n"
325" and %%r20, %%r19, %%r20\n"
326" andcm %%r21, %%r19, %%r21\n"
327" or %%r22, %%r20, %%r20\n"
328" or %%r1, %%r21, %%r21\n"
329"3: std %%r20,0(%%sr1,%2)\n"
330"4: std %%r21,8(%%sr1,%2)\n"
331"5: \n"
332 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
333 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
334 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
335 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
336 : "+r" (ret)
337 : "r" (val), "r" (regs->ior), "r" (regs->isr)
338 : "r19", "r20", "r21", "r22", "r1" );
339#else
340 {
341 __asm__ __volatile__ (
342" mtsp %3, %%sr1\n"
343" zdep %R1, 29, 2, %%r19\n"
344" dep %%r0, 31, 2, %2\n"
345" mtsar %%r19\n"
346" zvdepi -2, 32, %%r19\n"
347"1: ldw 0(%%sr1,%2),%%r20\n"
348"2: ldw 8(%%sr1,%2),%%r21\n"
349" vshd %1, %R1, %%r1\n"
350" vshd %%r0, %1, %1\n"
351" vshd %R1, %%r0, %R1\n"
352" and %%r20, %%r19, %%r20\n"
353" andcm %%r21, %%r19, %%r21\n"
354" or %1, %%r20, %1\n"
355" or %R1, %%r21, %R1\n"
356"3: stw %1,0(%%sr1,%2)\n"
357"4: stw %%r1,4(%%sr1,%2)\n"
358"5: stw %R1,8(%%sr1,%2)\n"
359"6: \n"
360 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
361 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
362 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
363 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
364 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
365 : "+r" (ret)
366 : "r" (val), "r" (regs->ior), "r" (regs->isr)
367 : "r19", "r20", "r21", "r1" );
368 }
369#endif
370
371 return ret;
372}
373
374void handle_unaligned(struct pt_regs *regs)
375{
376 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
377 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
378 int modify = 0;
379 int ret = ERR_NOTHANDLED;
380
381 __inc_irq_stat(irq_unaligned_count);
382 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->ior);
383
384 /* log a message with pacing */
385 if (user_mode(regs)) {
386 if (current->thread.flags & PARISC_UAC_SIGBUS) {
387 goto force_sigbus;
388 }
389
390 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
391 __ratelimit(&ratelimit)) {
392 printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
393 " at ip " RFMT " (iir " RFMT ")\n",
394 current->comm, task_pid_nr(current), regs->ior,
395 regs->iaoq[0], regs->iir);
396#ifdef DEBUG_UNALIGNED
397 show_regs(regs);
398#endif
399 }
400
401 if (!unaligned_enabled)
402 goto force_sigbus;
403 } else {
404 static DEFINE_RATELIMIT_STATE(kernel_ratelimit, 5 * HZ, 5);
405 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
406 !no_unaligned_warning &&
407 __ratelimit(&kernel_ratelimit))
408 pr_warn("Kernel: unaligned access to " RFMT " in %pS "
409 "(iir " RFMT ")\n",
410 regs->ior, (void *)regs->iaoq[0], regs->iir);
411 }
412
413 /* handle modification - OK, it's ugly, see the instruction manual */
414 switch (MAJOR_OP(regs->iir))
415 {
416 case 0x03:
417 case 0x09:
418 case 0x0b:
419 if (regs->iir&0x20)
420 {
421 modify = 1;
422 if (regs->iir&0x1000) /* short loads */
423 if (regs->iir&0x200)
424 newbase += IM5_3(regs->iir);
425 else
426 newbase += IM5_2(regs->iir);
427 else if (regs->iir&0x2000) /* scaled indexed */
428 {
429 int shift=0;
430 switch (regs->iir & OPCODE1_MASK)
431 {
432 case OPCODE_LDH_I:
433 shift= 1; break;
434 case OPCODE_LDW_I:
435 shift= 2; break;
436 case OPCODE_LDD_I:
437 case OPCODE_LDDA_I:
438 shift= 3; break;
439 }
440 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
441 } else /* simple indexed */
442 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
443 }
444 break;
445 case 0x13:
446 case 0x1b:
447 modify = 1;
448 newbase += IM14(regs->iir);
449 break;
450 case 0x14:
451 case 0x1c:
452 if (regs->iir&8)
453 {
454 modify = 1;
455 newbase += IM14(regs->iir&~0xe);
456 }
457 break;
458 case 0x16:
459 case 0x1e:
460 modify = 1;
461 newbase += IM14(regs->iir&6);
462 break;
463 case 0x17:
464 case 0x1f:
465 if (regs->iir&4)
466 {
467 modify = 1;
468 newbase += IM14(regs->iir&~4);
469 }
470 break;
471 }
472
473 /* TODO: make this cleaner... */
474 switch (regs->iir & OPCODE1_MASK)
475 {
476 case OPCODE_LDH_I:
477 case OPCODE_LDH_S:
478 ret = emulate_ldh(regs, R3(regs->iir));
479 break;
480
481 case OPCODE_LDW_I:
482 case OPCODE_LDWA_I:
483 case OPCODE_LDW_S:
484 case OPCODE_LDWA_S:
485 ret = emulate_ldw(regs, R3(regs->iir), 0);
486 break;
487
488 case OPCODE_STH:
489 ret = emulate_sth(regs, R2(regs->iir));
490 break;
491
492 case OPCODE_STW:
493 case OPCODE_STWA:
494 ret = emulate_stw(regs, R2(regs->iir), 0);
495 break;
496
497#ifdef CONFIG_64BIT
498 case OPCODE_LDD_I:
499 case OPCODE_LDDA_I:
500 case OPCODE_LDD_S:
501 case OPCODE_LDDA_S:
502 ret = emulate_ldd(regs, R3(regs->iir), 0);
503 break;
504
505 case OPCODE_STD:
506 case OPCODE_STDA:
507 ret = emulate_std(regs, R2(regs->iir), 0);
508 break;
509#endif
510
511 case OPCODE_FLDWX:
512 case OPCODE_FLDWS:
513 case OPCODE_FLDWXR:
514 case OPCODE_FLDWSR:
515 ret = emulate_ldw(regs, FR3(regs->iir), 1);
516 break;
517
518 case OPCODE_FLDDX:
519 case OPCODE_FLDDS:
520 ret = emulate_ldd(regs, R3(regs->iir), 1);
521 break;
522
523 case OPCODE_FSTWX:
524 case OPCODE_FSTWS:
525 case OPCODE_FSTWXR:
526 case OPCODE_FSTWSR:
527 ret = emulate_stw(regs, FR3(regs->iir), 1);
528 break;
529
530 case OPCODE_FSTDX:
531 case OPCODE_FSTDS:
532 ret = emulate_std(regs, R3(regs->iir), 1);
533 break;
534
535 case OPCODE_LDCD_I:
536 case OPCODE_LDCW_I:
537 case OPCODE_LDCD_S:
538 case OPCODE_LDCW_S:
539 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
540 break;
541 }
542 switch (regs->iir & OPCODE2_MASK)
543 {
544 case OPCODE_FLDD_L:
545 ret = emulate_ldd(regs,R2(regs->iir),1);
546 break;
547 case OPCODE_FSTD_L:
548 ret = emulate_std(regs, R2(regs->iir),1);
549 break;
550#ifdef CONFIG_64BIT
551 case OPCODE_LDD_L:
552 ret = emulate_ldd(regs, R2(regs->iir),0);
553 break;
554 case OPCODE_STD_L:
555 ret = emulate_std(regs, R2(regs->iir),0);
556 break;
557#endif
558 }
559 switch (regs->iir & OPCODE3_MASK)
560 {
561 case OPCODE_FLDW_L:
562 ret = emulate_ldw(regs, R2(regs->iir), 1);
563 break;
564 case OPCODE_LDW_M:
565 ret = emulate_ldw(regs, R2(regs->iir), 0);
566 break;
567
568 case OPCODE_FSTW_L:
569 ret = emulate_stw(regs, R2(regs->iir),1);
570 break;
571 case OPCODE_STW_M:
572 ret = emulate_stw(regs, R2(regs->iir),0);
573 break;
574 }
575 switch (regs->iir & OPCODE4_MASK)
576 {
577 case OPCODE_LDH_L:
578 ret = emulate_ldh(regs, R2(regs->iir));
579 break;
580 case OPCODE_LDW_L:
581 case OPCODE_LDWM:
582 ret = emulate_ldw(regs, R2(regs->iir),0);
583 break;
584 case OPCODE_STH_L:
585 ret = emulate_sth(regs, R2(regs->iir));
586 break;
587 case OPCODE_STW_L:
588 case OPCODE_STWM:
589 ret = emulate_stw(regs, R2(regs->iir),0);
590 break;
591 }
592
593 if (ret == 0 && modify && R1(regs->iir))
594 regs->gr[R1(regs->iir)] = newbase;
595
596
597 if (ret == ERR_NOTHANDLED)
598 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
599
600 DPRINTF("ret = %d\n", ret);
601
602 if (ret)
603 {
604 /*
605 * The unaligned handler failed.
606 * If we were called by __get_user() or __put_user() jump
607 * to it's exception fixup handler instead of crashing.
608 */
609 if (!user_mode(regs) && fixup_exception(regs))
610 return;
611
612 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
613 die_if_kernel("Unaligned data reference", regs, 28);
614
615 if (ret == -EFAULT)
616 {
617 force_sig_fault(SIGSEGV, SEGV_MAPERR,
618 (void __user *)regs->ior);
619 }
620 else
621 {
622force_sigbus:
623 /* couldn't handle it ... */
624 force_sig_fault(SIGBUS, BUS_ADRALN,
625 (void __user *)regs->ior);
626 }
627
628 return;
629 }
630
631 /* else we handled it, let life go on. */
632 regs->gr[0]|=PSW_N;
633}
634
635/*
636 * NB: check_unaligned() is only used for PCXS processors right
637 * now, so we only check for PA1.1 encodings at this point.
638 */
639
640int
641check_unaligned(struct pt_regs *regs)
642{
643 unsigned long align_mask;
644
645 /* Get alignment mask */
646
647 align_mask = 0UL;
648 switch (regs->iir & OPCODE1_MASK) {
649
650 case OPCODE_LDH_I:
651 case OPCODE_LDH_S:
652 case OPCODE_STH:
653 align_mask = 1UL;
654 break;
655
656 case OPCODE_LDW_I:
657 case OPCODE_LDWA_I:
658 case OPCODE_LDW_S:
659 case OPCODE_LDWA_S:
660 case OPCODE_STW:
661 case OPCODE_STWA:
662 align_mask = 3UL;
663 break;
664
665 default:
666 switch (regs->iir & OPCODE4_MASK) {
667 case OPCODE_LDH_L:
668 case OPCODE_STH_L:
669 align_mask = 1UL;
670 break;
671 case OPCODE_LDW_L:
672 case OPCODE_LDWM:
673 case OPCODE_STW_L:
674 case OPCODE_STWM:
675 align_mask = 3UL;
676 break;
677 }
678 break;
679 }
680
681 return (int)(regs->ior & align_mask);
682}
683