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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2#ifndef _ASM_POWERPC_PROCESSOR_H
3#define _ASM_POWERPC_PROCESSOR_H
4
5/*
6 * Copyright (C) 2001 PPC 64 Team, IBM Corp
7 */
8
9#include <vdso/processor.h>
10
11#include <asm/reg.h>
12
13#ifdef CONFIG_VSX
14#define TS_FPRWIDTH 2
15
16#ifdef __BIG_ENDIAN__
17#define TS_FPROFFSET 0
18#define TS_VSRLOWOFFSET 1
19#else
20#define TS_FPROFFSET 1
21#define TS_VSRLOWOFFSET 0
22#endif
23
24#else
25#define TS_FPRWIDTH 1
26#define TS_FPROFFSET 0
27#endif
28
29#ifdef CONFIG_PPC64
30/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
31#define PPR_PRIORITY 3
32#ifdef __ASSEMBLER__
33#define DEFAULT_PPR (PPR_PRIORITY << 50)
34#else
35#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
36#endif /* __ASSEMBLER__ */
37#endif /* CONFIG_PPC64 */
38
39#ifndef __ASSEMBLER__
40#include <linux/types.h>
41#include <linux/thread_info.h>
42#include <asm/ptrace.h>
43#include <asm/hw_breakpoint.h>
44
45/* We do _not_ want to define new machine types at all, those must die
46 * in favor of using the device-tree
47 * -- BenH.
48 */
49
50/* PREP sub-platform types. Unused */
51#define _PREP_Motorola 0x01 /* motorola prep */
52#define _PREP_Firm 0x02 /* firmworks prep */
53#define _PREP_IBM 0x00 /* ibm prep */
54#define _PREP_Bull 0x03 /* bull prep */
55
56/* CHRP sub-platform types. These are arbitrary */
57#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
58#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
59#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
60#define _CHRP_briq 0x07 /* TotalImpact's briQ */
61
62#if defined(__KERNEL__) && defined(CONFIG_PPC32)
63
64extern int _chrp_type;
65
66#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
67
68#ifdef __KERNEL__
69
70#ifdef CONFIG_PPC64
71#include <asm/task_size_64.h>
72#else
73#include <asm/task_size_32.h>
74#endif
75
76struct task_struct;
77void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
78
79#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
80#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
81
82/* FP and VSX 0-31 register set */
83struct thread_fp_state {
84 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
85 u64 fpscr; /* Floating point status */
86};
87
88/* Complete AltiVec register set including VSCR */
89struct thread_vr_state {
90 vector128 vr[32] __attribute__((aligned(16)));
91 vector128 vscr __attribute__((aligned(16)));
92};
93
94struct debug_reg {
95#ifdef CONFIG_PPC_ADV_DEBUG_REGS
96 /*
97 * The following help to manage the use of Debug Control Registers
98 * om the BookE platforms.
99 */
100 uint32_t dbcr0;
101 uint32_t dbcr1;
102#ifdef CONFIG_BOOKE
103 uint32_t dbcr2;
104#endif
105 /*
106 * The stored value of the DBSR register will be the value at the
107 * last debug interrupt. This register can only be read from the
108 * user (will never be written to) and has value while helping to
109 * describe the reason for the last debug trap. Torez
110 */
111 uint32_t dbsr;
112 /*
113 * The following will contain addresses used by debug applications
114 * to help trace and trap on particular address locations.
115 * The bits in the Debug Control Registers above help define which
116 * of the following registers will contain valid data and/or addresses.
117 */
118 unsigned long iac1;
119 unsigned long iac2;
120#if CONFIG_PPC_ADV_DEBUG_IACS > 2
121 unsigned long iac3;
122 unsigned long iac4;
123#endif
124 unsigned long dac1;
125 unsigned long dac2;
126#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
127 unsigned long dvc1;
128 unsigned long dvc2;
129#endif
130#endif
131};
132
133struct thread_struct {
134 unsigned long ksp; /* Kernel stack pointer */
135
136#ifdef CONFIG_PPC64
137 unsigned long ksp_vsid;
138#endif
139 struct pt_regs *regs; /* Pointer to saved register state */
140#ifdef CONFIG_BOOKE
141 /* BookE base exception scratch space; align on cacheline */
142 unsigned long normsave[8] ____cacheline_aligned;
143#endif
144#ifdef CONFIG_PPC32
145 void *pgdir; /* root of page-table tree */
146#ifdef CONFIG_PPC_RTAS
147 unsigned long rtas_sp; /* stack pointer for when in RTAS */
148#endif
149#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
150 unsigned long kuap; /* opened segments for user access */
151#endif
152 unsigned long srr0;
153 unsigned long srr1;
154 unsigned long dar;
155 unsigned long dsisr;
156#ifdef CONFIG_PPC_BOOK3S_32
157 unsigned long r0, r3, r4, r5, r6, r8, r9, r11;
158 unsigned long lr, ctr;
159 unsigned long sr0;
160#endif
161#endif /* CONFIG_PPC32 */
162#if defined(CONFIG_BOOKE) && defined(CONFIG_PPC_KUAP)
163 unsigned long pid; /* value written in PID reg. at interrupt exit */
164#endif
165 /* Debug Registers */
166 struct debug_reg debug;
167#ifdef CONFIG_PPC_FPU_REGS
168 struct thread_fp_state fp_state;
169 struct thread_fp_state *fp_save_area;
170#endif
171 int fpexc_mode; /* floating-point exception mode */
172 unsigned int align_ctl; /* alignment handling control */
173#ifdef CONFIG_HAVE_HW_BREAKPOINT
174 struct perf_event *ptrace_bps[HBP_NUM_MAX];
175#endif /* CONFIG_HAVE_HW_BREAKPOINT */
176 struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */
177 unsigned long trap_nr; /* last trap # on this thread */
178 u8 load_slb; /* Ages out SLB preload cache entries */
179 u8 load_fp;
180#ifdef CONFIG_ALTIVEC
181 u8 load_vec;
182 struct thread_vr_state vr_state;
183 struct thread_vr_state *vr_save_area;
184 unsigned long vrsave;
185 int used_vr; /* set if process has used altivec */
186#endif /* CONFIG_ALTIVEC */
187#ifdef CONFIG_VSX
188 /* VSR status */
189 int used_vsr; /* set if process has used VSX */
190#endif /* CONFIG_VSX */
191#ifdef CONFIG_SPE
192 struct_group(spe,
193 unsigned long evr[32]; /* upper 32-bits of SPE regs */
194 u64 acc; /* Accumulator */
195 );
196 unsigned long spefscr; /* SPE & eFP status */
197 unsigned long spefscr_last; /* SPEFSCR value on last prctl
198 call or trap return */
199 int used_spe; /* set if process has used spe */
200#endif /* CONFIG_SPE */
201#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
202 u8 load_tm;
203 u64 tm_tfhar; /* Transaction fail handler addr */
204 u64 tm_texasr; /* Transaction exception & summary */
205 u64 tm_tfiar; /* Transaction fail instr address reg */
206 struct pt_regs ckpt_regs; /* Checkpointed registers */
207
208 unsigned long tm_tar;
209 unsigned long tm_ppr;
210 unsigned long tm_dscr;
211 unsigned long tm_amr;
212
213 /*
214 * Checkpointed FP and VSX 0-31 register set.
215 *
216 * When a transaction is active/signalled/scheduled etc., *regs is the
217 * most recent set of/speculated GPRs with ckpt_regs being the older
218 * checkpointed regs to which we roll back if transaction aborts.
219 *
220 * These are analogous to how ckpt_regs and pt_regs work
221 */
222 struct thread_fp_state ckfp_state; /* Checkpointed FP state */
223 struct thread_vr_state ckvr_state; /* Checkpointed VR state */
224 unsigned long ckvrsave; /* Checkpointed VRSAVE */
225#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
226#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
227 void* kvm_shadow_vcpu; /* KVM internal data */
228#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
229#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
230 struct kvm_vcpu *kvm_vcpu;
231#endif
232#ifdef CONFIG_PPC64
233 unsigned long dscr;
234 unsigned long fscr;
235 /*
236 * This member element dscr_inherit indicates that the process
237 * has explicitly attempted and changed the DSCR register value
238 * for itself. Hence kernel wont use the default CPU DSCR value
239 * contained in the PACA structure anymore during process context
240 * switch. Once this variable is set, this behaviour will also be
241 * inherited to all the children of this process from that point
242 * onwards.
243 */
244 int dscr_inherit;
245 unsigned long tidr;
246#endif
247#ifdef CONFIG_PPC_BOOK3S_64
248 unsigned long tar;
249 unsigned long ebbrr;
250 unsigned long ebbhr;
251 unsigned long bescr;
252 unsigned long siar;
253 unsigned long sdar;
254 unsigned long sier;
255 unsigned long mmcr2;
256 unsigned mmcr0;
257
258 unsigned used_ebb;
259 unsigned long mmcr3;
260 unsigned long sier2;
261 unsigned long sier3;
262 unsigned long hashkeyr;
263 unsigned long dexcr;
264 unsigned long dexcr_onexec; /* Reset value to load on exec */
265#endif
266};
267
268#define ARCH_MIN_TASKALIGN 16
269
270#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
271#define INIT_SP_LIMIT ((unsigned long)&init_stack)
272
273#ifdef CONFIG_SPE
274#define SPEFSCR_INIT \
275 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
276 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
277#else
278#define SPEFSCR_INIT
279#endif
280
281#ifdef CONFIG_PPC_BOOK3S_32
282#define SR0_INIT .sr0 = IS_ENABLED(CONFIG_PPC_KUEP) ? SR_NX : 0,
283#else
284#define SR0_INIT
285#endif
286
287#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
288#define INIT_THREAD { \
289 .ksp = INIT_SP, \
290 .pgdir = swapper_pg_dir, \
291 .kuap = ~0UL, /* KUAP_NONE */ \
292 .fpexc_mode = MSR_FE0 | MSR_FE1, \
293 SPEFSCR_INIT \
294 SR0_INIT \
295}
296#elif defined(CONFIG_PPC32)
297#define INIT_THREAD { \
298 .ksp = INIT_SP, \
299 .pgdir = swapper_pg_dir, \
300 .fpexc_mode = MSR_FE0 | MSR_FE1, \
301 SPEFSCR_INIT \
302 SR0_INIT \
303}
304#else
305#define INIT_THREAD { \
306 .ksp = INIT_SP, \
307 .fpexc_mode = 0, \
308}
309#endif
310
311#define task_pt_regs(tsk) ((tsk)->thread.regs)
312
313unsigned long __get_wchan(struct task_struct *p);
314
315#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
316#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
317
318/* Get/set floating-point exception mode */
319#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
320#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
321
322extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
323extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
324
325#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
326#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
327
328extern int get_endian(struct task_struct *tsk, unsigned long adr);
329extern int set_endian(struct task_struct *tsk, unsigned int val);
330
331#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
332#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
333
334extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
335extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
336
337#ifdef CONFIG_PPC_BOOK3S_64
338
339#define PPC_GET_DEXCR_ASPECT(tsk, asp) get_dexcr_prctl((tsk), (asp))
340#define PPC_SET_DEXCR_ASPECT(tsk, asp, val) set_dexcr_prctl((tsk), (asp), (val))
341
342int get_dexcr_prctl(struct task_struct *tsk, unsigned long asp);
343int set_dexcr_prctl(struct task_struct *tsk, unsigned long asp, unsigned long val);
344
345#endif
346
347extern void load_fp_state(struct thread_fp_state *fp);
348extern void store_fp_state(struct thread_fp_state *fp);
349extern void load_vr_state(struct thread_vr_state *vr);
350extern void store_vr_state(struct thread_vr_state *vr);
351
352static inline unsigned int __unpack_fe01(unsigned long msr_bits)
353{
354 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
355}
356
357static inline unsigned long __pack_fe01(unsigned int fpmode)
358{
359 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
360}
361
362#ifdef CONFIG_PPC64
363
364#define spin_begin() \
365 asm volatile(ASM_FTR_IFCLR( \
366 "or 1,1,1", /* HMT_LOW */ \
367 "nop", /* v3.1 uses pause_short in cpu_relax instead */ \
368 %0) :: "i" (CPU_FTR_ARCH_31) : "memory")
369
370#define spin_cpu_relax() \
371 asm volatile(ASM_FTR_IFCLR( \
372 "nop", /* Before v3.1 use priority nops in spin_begin/end */ \
373 PPC_WAIT(2, 0), /* aka pause_short */ \
374 %0) :: "i" (CPU_FTR_ARCH_31) : "memory")
375
376#define spin_end() \
377 asm volatile(ASM_FTR_IFCLR( \
378 "or 2,2,2", /* HMT_MEDIUM */ \
379 "nop", \
380 %0) :: "i" (CPU_FTR_ARCH_31) : "memory")
381
382#endif
383
384/*
385 * Check that a certain kernel stack pointer is a valid (minimum sized)
386 * stack frame in task_struct p.
387 */
388int validate_sp(unsigned long sp, struct task_struct *p);
389
390/*
391 * validate the stack frame of a particular minimum size, used for when we are
392 * looking at a certain object in the stack beyond the minimum.
393 */
394int validate_sp_size(unsigned long sp, struct task_struct *p,
395 unsigned long nbytes);
396
397/*
398 * Prefetch macros.
399 */
400#define ARCH_HAS_PREFETCH
401#define ARCH_HAS_PREFETCHW
402
403static inline void prefetch(const void *x)
404{
405 if (unlikely(!x))
406 return;
407
408 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
409}
410
411static inline void prefetchw(const void *x)
412{
413 if (unlikely(!x))
414 return;
415
416 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
417}
418
419/* asm stubs */
420extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
421extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
422extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
423#ifdef CONFIG_PPC_970_NAP
424extern void power4_idle_nap(void);
425void power4_idle_nap_return(void);
426#endif
427
428extern unsigned long cpuidle_disable;
429enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
430
431extern int powersave_nap; /* set if nap mode can be used in idle loop */
432
433extern void power7_idle_type(unsigned long type);
434extern void arch300_idle_type(unsigned long stop_psscr_val,
435 unsigned long stop_psscr_mask);
436void pnv_power9_force_smt4_catch(void);
437void pnv_power9_force_smt4_release(void);
438
439extern int fix_alignment(struct pt_regs *);
440
441#ifdef CONFIG_PPC64
442/*
443 * We handle most unaligned accesses in hardware. On the other hand
444 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
445 * powers of 2 writes until it reaches sufficient alignment).
446 *
447 * Based on this we disable the IP header alignment in network drivers.
448 */
449#define NET_IP_ALIGN 0
450#endif
451
452int do_mathemu(struct pt_regs *regs);
453int do_spe_mathemu(struct pt_regs *regs);
454int speround_handler(struct pt_regs *regs);
455
456/* VMX copying */
457int enter_vmx_usercopy(void);
458int exit_vmx_usercopy(void);
459int enter_vmx_ops(void);
460void *exit_vmx_ops(void *dest);
461
462#endif /* __KERNEL__ */
463#endif /* __ASSEMBLER__ */
464#endif /* _ASM_POWERPC_PROCESSOR_H */