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| 2 | #ifndef _ASM_POWERPC_AUXVEC_H
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| 3 | #define _ASM_POWERPC_AUXVEC_H
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| 4 |
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| 5 | |
| 6 | * We need to put in some extra aux table entries to tell glibc what
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| 7 | * the cache block size is, so it can use the dcbz instruction safely.
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| 8 |
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| 9 | #define AT_DCACHEBSIZE 19
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| 10 | #define AT_ICACHEBSIZE 20
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| 11 | #define AT_UCACHEBSIZE 21
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| 12 |
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| 13 | #define AT_IGNOREPPC 22
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| 14 |
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| 15 | |
| 16 | * sake :-)
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| 17 |
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| 18 | #define AT_SYSINFO_EHDR 33
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| 19 |
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| 20 | |
| 21 | * AT_*CACHEBSIZE above represent the cache *block* size which is
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| 22 | * the size that is affected by the cache management instructions.
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| 23 | *
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| 24 | * It doesn't nececssarily matches the cache *line* size which is
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| 25 | * more of a performance tuning hint. Additionally the latter can
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| 26 | * be different for the different cache levels.
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| 27 | *
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| 28 | * The set of entries below represent more extensive information
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| 29 | * about the caches, in the form of two entry per cache type,
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| 30 | * one entry containing the cache size in bytes, and the other
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| 31 | * containing the cache line size in bytes in the bottom 16 bits
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| 32 | * and the cache associativity in the next 16 bits.
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| 33 | *
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| 34 | * The associativity is such that if N is the 16-bit value, the
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| 35 | * cache is N way set associative. A value if 0xffff means fully
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| 36 | * associative, a value of 1 means directly mapped.
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| 37 | *
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| 38 | * For all these fields, a value of 0 means that the information
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| 39 | * is not known.
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| 40 |
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| 41 |
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| 42 | #define AT_L1I_CACHESIZE 40
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| 43 | #define AT_L1I_CACHEGEOMETRY 41
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| 44 | #define AT_L1D_CACHESIZE 42
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| 45 | #define AT_L1D_CACHEGEOMETRY 43
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| 46 | #define AT_L2_CACHESIZE 44
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| 47 | #define AT_L2_CACHEGEOMETRY 45
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| 48 | #define AT_L3_CACHESIZE 46
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| 49 | #define AT_L3_CACHEGEOMETRY 47
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| 50 |
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| 51 | #define AT_MINSIGSTKSZ 51
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| 52 |
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| 53 | #define AT_VECTOR_SIZE_ARCH 15
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| 54 |
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| 55 | #endif
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