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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright IBM Corp. 2007
4 *
5 * Authors: Hollis Blanchard <[email protected]>
6 */
7
8#ifndef __LINUX_KVM_POWERPC_H
9#define __LINUX_KVM_POWERPC_H
10
11#include <linux/types.h>
12
13/* Select powerpc specific features in <linux/kvm.h> */
14#define __KVM_HAVE_SPAPR_TCE
15#define __KVM_HAVE_PPC_SMT
16#define __KVM_HAVE_IRQCHIP
17#define __KVM_HAVE_IRQ_LINE
18
19/* Not always available, but if it is, this is the correct offset. */
20#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
21
22struct kvm_regs {
23 __u64 pc;
24 __u64 cr;
25 __u64 ctr;
26 __u64 lr;
27 __u64 xer;
28 __u64 msr;
29 __u64 srr0;
30 __u64 srr1;
31 __u64 pid;
32
33 __u64 sprg0;
34 __u64 sprg1;
35 __u64 sprg2;
36 __u64 sprg3;
37 __u64 sprg4;
38 __u64 sprg5;
39 __u64 sprg6;
40 __u64 sprg7;
41
42 __u64 gpr[32];
43};
44
45#define KVM_SREGS_E_IMPL_NONE 0
46#define KVM_SREGS_E_IMPL_FSL 1
47
48#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */
49
50/* flags for kvm_run.flags */
51#define KVM_RUN_PPC_NMI_DISP_MASK (3 << 0)
52#define KVM_RUN_PPC_NMI_DISP_FULLY_RECOV (1 << 0)
53#define KVM_RUN_PPC_NMI_DISP_LIMITED_RECOV (2 << 0)
54#define KVM_RUN_PPC_NMI_DISP_NOT_RECOV (3 << 0)
55
56/*
57 * Feature bits indicate which sections of the sregs struct are valid,
58 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers
59 * corresponding to unset feature bits will not be modified. This allows
60 * restoring a checkpoint made without that feature, while keeping the
61 * default values of the new registers.
62 *
63 * KVM_SREGS_E_BASE contains:
64 * CSRR0/1 (refers to SRR2/3 on 40x)
65 * ESR
66 * DEAR
67 * MCSR
68 * TSR
69 * TCR
70 * DEC
71 * TB
72 * VRSAVE (USPRG0)
73 */
74#define KVM_SREGS_E_BASE (1 << 0)
75
76/*
77 * KVM_SREGS_E_ARCH206 contains:
78 *
79 * PIR
80 * MCSRR0/1
81 * DECAR
82 * IVPR
83 */
84#define KVM_SREGS_E_ARCH206 (1 << 1)
85
86/*
87 * Contains EPCR, plus the upper half of 64-bit registers
88 * that are 32-bit on 32-bit implementations.
89 */
90#define KVM_SREGS_E_64 (1 << 2)
91
92#define KVM_SREGS_E_SPRG8 (1 << 3)
93#define KVM_SREGS_E_MCIVPR (1 << 4)
94
95/*
96 * IVORs are used -- contains IVOR0-15, plus additional IVORs
97 * in combination with an appropriate feature bit.
98 */
99#define KVM_SREGS_E_IVOR (1 << 5)
100
101/*
102 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
103 * Also TLBnPS if MMUCFG[MAVN] = 1.
104 */
105#define KVM_SREGS_E_ARCH206_MMU (1 << 6)
106
107/* DBSR, DBCR, IAC, DAC, DVC */
108#define KVM_SREGS_E_DEBUG (1 << 7)
109
110/* Enhanced debug -- DSRR0/1, SPRG9 */
111#define KVM_SREGS_E_ED (1 << 8)
112
113/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
114#define KVM_SREGS_E_SPE (1 << 9)
115
116/*
117 * DEPRECATED! USE ONE_REG FOR THIS ONE!
118 * External Proxy (EXP) -- EPR
119 */
120#define KVM_SREGS_EXP (1 << 10)
121
122/* External PID (E.PD) -- EPSC/EPLC */
123#define KVM_SREGS_E_PD (1 << 11)
124
125/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
126#define KVM_SREGS_E_PC (1 << 12)
127
128/* Page table (E.PT) -- EPTCFG */
129#define KVM_SREGS_E_PT (1 << 13)
130
131/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
132#define KVM_SREGS_E_PM (1 << 14)
133
134/*
135 * Special updates:
136 *
137 * Some registers may change even while a vcpu is not running.
138 * To avoid losing these changes, by default these registers are
139 * not updated by KVM_SET_SREGS. To force an update, set the bit
140 * in u.e.update_special corresponding to the register to be updated.
141 *
142 * The update_special field is zero on return from KVM_GET_SREGS.
143 *
144 * When restoring a checkpoint, the caller can set update_special
145 * to 0xffffffff to ensure that everything is restored, even new features
146 * that the caller doesn't know about.
147 */
148#define KVM_SREGS_E_UPDATE_MCSR (1 << 0)
149#define KVM_SREGS_E_UPDATE_TSR (1 << 1)
150#define KVM_SREGS_E_UPDATE_DEC (1 << 2)
151#define KVM_SREGS_E_UPDATE_DBSR (1 << 3)
152
153/*
154 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
155 * previous KVM_GET_REGS.
156 *
157 * Unless otherwise indicated, setting any register with KVM_SET_SREGS
158 * directly sets its value. It does not trigger any special semantics such
159 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct
160 * just received from KVM_GET_SREGS is always a no-op.
161 */
162struct kvm_sregs {
163 __u32 pvr;
164 union {
165 struct {
166 __u64 sdr1;
167 struct {
168 struct {
169 __u64 slbe;
170 __u64 slbv;
171 } slb[64];
172 } ppc64;
173 struct {
174 __u32 sr[16];
175 __u64 ibat[8];
176 __u64 dbat[8];
177 } ppc32;
178 } s;
179 struct {
180 union {
181 struct { /* KVM_SREGS_E_IMPL_FSL */
182 __u32 features; /* KVM_SREGS_E_FSL_ */
183 __u32 svr;
184 __u64 mcar;
185 __u32 hid0;
186
187 /* KVM_SREGS_E_FSL_PIDn */
188 __u32 pid1, pid2;
189 } fsl;
190 __u8 pad[256];
191 } impl;
192
193 __u32 features; /* KVM_SREGS_E_ */
194 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */
195 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */
196 __u32 pir; /* read-only */
197 __u64 sprg8;
198 __u64 sprg9; /* E.ED */
199 __u64 csrr0;
200 __u64 dsrr0; /* E.ED */
201 __u64 mcsrr0;
202 __u32 csrr1;
203 __u32 dsrr1; /* E.ED */
204 __u32 mcsrr1;
205 __u32 esr;
206 __u64 dear;
207 __u64 ivpr;
208 __u64 mcivpr;
209 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */
210
211 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */
212 __u32 tcr;
213 __u32 decar;
214 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */
215
216 /*
217 * Userspace can read TB directly, but the
218 * value reported here is consistent with "dec".
219 *
220 * Read-only.
221 */
222 __u64 tb;
223
224 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */
225 __u32 dbcr[3];
226 /*
227 * iac/dac registers are 64bit wide, while this API
228 * interface provides only lower 32 bits on 64 bit
229 * processors. ONE_REG interface is added for 64bit
230 * iac/dac registers.
231 */
232 __u32 iac[4];
233 __u32 dac[2];
234 __u32 dvc[2];
235 __u8 num_iac; /* read-only */
236 __u8 num_dac; /* read-only */
237 __u8 num_dvc; /* read-only */
238 __u8 pad;
239
240 __u32 epr; /* EXP */
241 __u32 vrsave; /* a.k.a. USPRG0 */
242 __u32 epcr; /* KVM_SREGS_E_64 */
243
244 __u32 mas0;
245 __u32 mas1;
246 __u64 mas2;
247 __u64 mas7_3;
248 __u32 mas4;
249 __u32 mas6;
250
251 __u32 ivor_low[16]; /* IVOR0-15 */
252 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */
253
254 __u32 mmucfg; /* read-only */
255 __u32 eptcfg; /* E.PT, read-only */
256 __u32 tlbcfg[4];/* read-only */
257 __u32 tlbps[4]; /* read-only */
258
259 __u32 eplc, epsc; /* E.PD */
260 } e;
261 __u8 pad[1020];
262 } u;
263};
264
265struct kvm_fpu {
266 __u64 fpr[32];
267};
268
269/*
270 * Defines for h/w breakpoint, watchpoint (read, write or both) and
271 * software breakpoint.
272 * These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status"
273 * for KVM_DEBUG_EXIT.
274 */
275#define KVMPPC_DEBUG_NONE 0x0
276#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1)
277#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2)
278#define KVMPPC_DEBUG_WATCH_READ (1UL << 3)
279struct kvm_debug_exit_arch {
280 __u64 address;
281 /*
282 * exiting to userspace because of h/w breakpoint, watchpoint
283 * (read, write or both) and software breakpoint.
284 */
285 __u32 status;
286 __u32 reserved;
287};
288
289/* for KVM_SET_GUEST_DEBUG */
290struct kvm_guest_debug_arch {
291 struct {
292 /* H/W breakpoint/watchpoint address */
293 __u64 addr;
294 /*
295 * Type denotes h/w breakpoint, read watchpoint, write
296 * watchpoint or watchpoint (both read and write).
297 */
298 __u32 type;
299 __u32 reserved;
300 } bp[16];
301};
302
303/* Debug related defines */
304/*
305 * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
306 * and upper 16 bits are architecture specific. Architecture specific defines
307 * that ioctl is for setting hardware breakpoint or software breakpoint.
308 */
309#define KVM_GUESTDBG_USE_SW_BP 0x00010000
310#define KVM_GUESTDBG_USE_HW_BP 0x00020000
311
312/* definition of registers in kvm_run */
313struct kvm_sync_regs {
314};
315
316#define KVM_INTERRUPT_SET -1U
317#define KVM_INTERRUPT_UNSET -2U
318#define KVM_INTERRUPT_SET_LEVEL -3U
319
320#define KVM_CPU_440 1
321#define KVM_CPU_E500V2 2
322#define KVM_CPU_3S_32 3
323#define KVM_CPU_3S_64 4
324#define KVM_CPU_E500MC 5
325
326/* for KVM_CAP_SPAPR_TCE */
327struct kvm_create_spapr_tce {
328 __u64 liobn;
329 __u32 window_size;
330};
331
332/* for KVM_CAP_SPAPR_TCE_64 */
333struct kvm_create_spapr_tce_64 {
334 __u64 liobn;
335 __u32 page_shift;
336 __u32 flags;
337 __u64 offset; /* in pages */
338 __u64 size; /* in pages */
339};
340
341/* for KVM_ALLOCATE_RMA */
342struct kvm_allocate_rma {
343 __u64 rma_size;
344};
345
346/* for KVM_CAP_PPC_RTAS */
347struct kvm_rtas_token_args {
348 char name[120];
349 __u64 token; /* Use a token of 0 to undefine a mapping */
350};
351
352struct kvm_book3e_206_tlb_entry {
353 __u32 mas8;
354 __u32 mas1;
355 __u64 mas2;
356 __u64 mas7_3;
357};
358
359struct kvm_book3e_206_tlb_params {
360 /*
361 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
362 *
363 * - The number of ways of TLB0 must be a power of two between 2 and
364 * 16.
365 * - TLB1 must be fully associative.
366 * - The size of TLB0 must be a multiple of the number of ways, and
367 * the number of sets must be a power of two.
368 * - The size of TLB1 may not exceed 64 entries.
369 * - TLB0 supports 4 KiB pages.
370 * - The page sizes supported by TLB1 are as indicated by
371 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
372 * as returned by KVM_GET_SREGS.
373 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
374 * and tlb_ways[] must be zero.
375 *
376 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
377 *
378 * KVM will adjust TLBnCFG based on the sizes configured here,
379 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
380 * set to zero.
381 */
382 __u32 tlb_sizes[4];
383 __u32 tlb_ways[4];
384 __u32 reserved[8];
385};
386
387/* For KVM_PPC_GET_HTAB_FD */
388struct kvm_get_htab_fd {
389 __u64 flags;
390 __u64 start_index;
391 __u64 reserved[2];
392};
393
394/* Values for kvm_get_htab_fd.flags */
395#define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1)
396#define KVM_GET_HTAB_WRITE ((__u64)0x2)
397
398/*
399 * Data read on the file descriptor is formatted as a series of
400 * records, each consisting of a header followed by a series of
401 * `n_valid' HPTEs (16 bytes each), which are all valid. Following
402 * those valid HPTEs there are `n_invalid' invalid HPTEs, which
403 * are not represented explicitly in the stream. The same format
404 * is used for writing.
405 */
406struct kvm_get_htab_header {
407 __u32 index;
408 __u16 n_valid;
409 __u16 n_invalid;
410};
411
412/* For KVM_PPC_CONFIGURE_V3_MMU */
413struct kvm_ppc_mmuv3_cfg {
414 __u64 flags;
415 __u64 process_table; /* second doubleword of partition table entry */
416};
417
418/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
419#define KVM_PPC_MMUV3_RADIX 1 /* 1 = radix mode, 0 = HPT */
420#define KVM_PPC_MMUV3_GTSE 2 /* global translation shootdown enb. */
421
422/* For KVM_PPC_GET_RMMU_INFO */
423struct kvm_ppc_rmmu_info {
424 struct kvm_ppc_radix_geom {
425 __u8 page_shift;
426 __u8 level_bits[4];
427 __u8 pad[3];
428 } geometries[8];
429 __u32 ap_encodings[8];
430};
431
432/* For KVM_PPC_GET_CPU_CHAR */
433struct kvm_ppc_cpu_char {
434 __u64 character; /* characteristics of the CPU */
435 __u64 behaviour; /* recommended software behaviour */
436 __u64 character_mask; /* valid bits in character */
437 __u64 behaviour_mask; /* valid bits in behaviour */
438};
439
440/* For KVM_PPC_GET_COMPAT_CAPS */
441struct kvm_ppc_compat_caps {
442 __u64 size; /* Size of this structure */
443 __u64 flags; /* Reserved for future use */
444 __u64 compat_capabilities; /* Capabilities supported by the host */
445};
446#define KVM_PPC_COMPAT_CAPS_SIZE_VER0 24 /* sizeof first published struct */
447
448/*
449 * Capability bits for compat_capabilities field in kvm_ppc_compat_caps.
450 * These bits indicate which processor compatibility modes are supported.
451 */
452#define KVM_PPC_COMPAT_CAP_POWER9 (1ULL << 62)
453#define KVM_PPC_COMPAT_CAP_POWER10 (1ULL << 61)
454#define KVM_PPC_COMPAT_CAP_POWER11 (1ULL << 60)
455#define KVM_PPC_COMPAT_BITMASK (KVM_PPC_COMPAT_CAP_POWER9 | \
456 KVM_PPC_COMPAT_CAP_POWER10 | \
457 KVM_PPC_COMPAT_CAP_POWER11)
458/*
459 * Values for character and character_mask.
460 * These are identical to the values used by H_GET_CPU_CHARACTERISTICS.
461 */
462#define KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31 (1ULL << 63)
463#define KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED (1ULL << 62)
464#define KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30 (1ULL << 61)
465#define KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2 (1ULL << 60)
466#define KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV (1ULL << 59)
467#define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED (1ULL << 58)
468#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF (1ULL << 57)
469#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS (1ULL << 56)
470#define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54)
471
472#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY (1ULL << 63)
473#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR (1ULL << 62)
474#define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ULL << 61)
475#define KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE (1ull << 58)
476
477/* Per-vcpu XICS interrupt controller state */
478#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
479
480#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */
481#define KVM_REG_PPC_ICP_CPPR_MASK 0xff
482#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */
483#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff
484#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */
485#define KVM_REG_PPC_ICP_MFRR_MASK 0xff
486#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */
487#define KVM_REG_PPC_ICP_PPRI_MASK 0xff
488
489#define KVM_REG_PPC_VP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x8d)
490
491/* Device control API: PPC-specific devices */
492#define KVM_DEV_MPIC_GRP_MISC 1
493#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
494
495#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */
496#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */
497
498/* One-Reg API: PPC-specific registers */
499#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
500#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
501#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
502#define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4)
503#define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5)
504#define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6)
505#define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7)
506#define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8)
507#define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9)
508#define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa)
509#define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb)
510#define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc)
511#define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd)
512#define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe)
513#define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf)
514
515#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
516#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
517#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
518#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
519#define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14)
520#define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15)
521#define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16)
522#define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17)
523
524#define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18)
525#define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19)
526#define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a)
527#define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b)
528#define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c)
529#define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d)
530#define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e)
531#define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f)
532
533/* 32 floating-point registers */
534#define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20)
535#define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n))
536#define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f)
537
538/* 32 VMX/Altivec vector registers */
539#define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40)
540#define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n))
541#define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f)
542
543/* 32 double-width FP registers for VSX */
544/* High-order halves overlap with FP regs */
545#define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60)
546#define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n))
547#define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f)
548
549/* FP and vector status/control registers */
550#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
551/*
552 * VSCR register is documented as a 32-bit register in the ISA, but it can
553 * only be accesses via a vector register. Expose VSCR as a 32-bit register
554 * even though the kernel represents it as a 128-bit vector.
555 */
556#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
557
558/* Virtual processor areas */
559/* For SLB & DTL, address in high (first) half, length in low half */
560#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82)
561#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
562#define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84)
563
564#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
565#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
566
567/* Timer Status Register OR/CLEAR interface */
568#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
569#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
570#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
571#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
572
573/* Debugging: Special instruction for software breakpoint */
574#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
575
576/* MMU registers */
577#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
578#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
579#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
580#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
581#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
582#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
583#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
584/*
585 * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
586 * KVM_CAP_SW_TLB ioctl
587 */
588#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
589#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
590#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
591#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
592#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
593#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
594#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
595#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
596#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
597
598/* Timebase offset */
599#define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c)
600
601/* POWER8 registers */
602#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d)
603#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e)
604#define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f)
605#define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0)
606#define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1)
607#define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2)
608#define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3)
609#define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4)
610#define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5)
611#define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6)
612#define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7)
613#define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8)
614#define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9)
615#define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa)
616#define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab)
617#define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac)
618#define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad)
619#define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae)
620#define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf)
621#define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0)
622#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
623#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
624#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
625
626#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
627#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
628#define KVM_REG_PPC_LPCR_64 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5)
629#define KVM_REG_PPC_PPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6)
630
631/* Architecture compatibility level */
632#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
633
634#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
635#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9)
636#define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
637#define KVM_REG_PPC_DBSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
638
639/* POWER9 registers */
640#define KVM_REG_PPC_TIDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
641#define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
642
643#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
644#define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
645#define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0)
646
647/* POWER10 registers */
648#define KVM_REG_PPC_MMCR3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1)
649#define KVM_REG_PPC_SIER2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2)
650#define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
651#define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
652#define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
653#define KVM_REG_PPC_DEXCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6)
654#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc7)
655#define KVM_REG_PPC_HASHPKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc8)
656
657/* Transactional Memory checkpointed state:
658 * This is all GPRs, all VSX regs and a subset of SPRs
659 */
660#define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000)
661/* TM GPRs */
662#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0)
663#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n))
664#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f)
665/* TM VSX */
666#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20)
667#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n))
668#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f)
669/* TM SPRS */
670#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60)
671#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61)
672#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62)
673#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63)
674#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64)
675#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65)
676#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66)
677#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
678#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
679#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
680#define KVM_REG_PPC_TM_XER (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
681
682/* PPC64 eXternal Interrupt Controller Specification */
683#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
684#define KVM_DEV_XICS_GRP_CTRL 2
685#define KVM_DEV_XICS_NR_SERVERS 1
686
687/* Layout of 64-bit source attribute values */
688#define KVM_XICS_DESTINATION_SHIFT 0
689#define KVM_XICS_DESTINATION_MASK 0xffffffffULL
690#define KVM_XICS_PRIORITY_SHIFT 32
691#define KVM_XICS_PRIORITY_MASK 0xff
692#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40)
693#define KVM_XICS_MASKED (1ULL << 41)
694#define KVM_XICS_PENDING (1ULL << 42)
695#define KVM_XICS_PRESENTED (1ULL << 43)
696#define KVM_XICS_QUEUED (1ULL << 44)
697
698/* POWER9 XIVE Native Interrupt Controller */
699#define KVM_DEV_XIVE_GRP_CTRL 1
700#define KVM_DEV_XIVE_RESET 1
701#define KVM_DEV_XIVE_EQ_SYNC 2
702#define KVM_DEV_XIVE_NR_SERVERS 3
703#define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */
704#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
705#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
706#define KVM_DEV_XIVE_GRP_SOURCE_SYNC 5 /* 64-bit source identifier */
707
708/* Layout of 64-bit XIVE source attribute values */
709#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
710#define KVM_XIVE_LEVEL_ASSERTED (1ULL << 1)
711
712/* Layout of 64-bit XIVE source configuration attribute values */
713#define KVM_XIVE_SOURCE_PRIORITY_SHIFT 0
714#define KVM_XIVE_SOURCE_PRIORITY_MASK 0x7
715#define KVM_XIVE_SOURCE_SERVER_SHIFT 3
716#define KVM_XIVE_SOURCE_SERVER_MASK 0xfffffff8ULL
717#define KVM_XIVE_SOURCE_MASKED_SHIFT 32
718#define KVM_XIVE_SOURCE_MASKED_MASK 0x100000000ULL
719#define KVM_XIVE_SOURCE_EISN_SHIFT 33
720#define KVM_XIVE_SOURCE_EISN_MASK 0xfffffffe00000000ULL
721
722/* Layout of 64-bit EQ identifier */
723#define KVM_XIVE_EQ_PRIORITY_SHIFT 0
724#define KVM_XIVE_EQ_PRIORITY_MASK 0x7
725#define KVM_XIVE_EQ_SERVER_SHIFT 3
726#define KVM_XIVE_EQ_SERVER_MASK 0xfffffff8ULL
727
728/* Layout of EQ configuration values (64 bytes) */
729struct kvm_ppc_xive_eq {
730 __u32 flags;
731 __u32 qshift;
732 __u64 qaddr;
733 __u32 qtoggle;
734 __u32 qindex;
735 __u8 pad[40];
736};
737
738#define KVM_XIVE_EQ_ALWAYS_NOTIFY 0x00000001
739
740#define KVM_XIVE_TIMA_PAGE_OFFSET 0
741#define KVM_XIVE_ESB_PAGE_OFFSET 4
742
743/* for KVM_PPC_GET_PVINFO */
744
745#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
746
747struct kvm_ppc_pvinfo {
748 /* out */
749 __u32 flags;
750 __u32 hcall[4];
751 __u8 pad[108];
752};
753
754/* for KVM_PPC_GET_SMMU_INFO */
755#define KVM_PPC_PAGE_SIZES_MAX_SZ 8
756
757struct kvm_ppc_one_page_size {
758 __u32 page_shift; /* Page shift (or 0) */
759 __u32 pte_enc; /* Encoding in the HPTE (>>12) */
760};
761
762struct kvm_ppc_one_seg_page_size {
763 __u32 page_shift; /* Base page shift of segment (or 0) */
764 __u32 slb_enc; /* SLB encoding for BookS */
765 struct kvm_ppc_one_page_size enc[KVM_PPC_PAGE_SIZES_MAX_SZ];
766};
767
768#define KVM_PPC_PAGE_SIZES_REAL 0x00000001
769#define KVM_PPC_1T_SEGMENTS 0x00000002
770#define KVM_PPC_NO_HASH 0x00000004
771
772struct kvm_ppc_smmu_info {
773 __u64 flags;
774 __u32 slb_size;
775 __u16 data_keys; /* # storage keys supported for data */
776 __u16 instr_keys; /* # storage keys supported for instructions */
777 struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ];
778};
779
780/* for KVM_PPC_RESIZE_HPT_{PREPARE,COMMIT} */
781struct kvm_ppc_resize_hpt {
782 __u64 flags;
783 __u32 shift;
784 __u32 pad;
785};
786
787#endif /* __LINUX_KVM_POWERPC_H */