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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * IPIC private definitions and structure.
4 *
5 * Maintainer: Kumar Gala <[email protected]>
6 *
7 * Copyright 2005 Freescale Semiconductor, Inc
8 */
9#ifndef __IPIC_H__
10#define __IPIC_H__
11
12#include <asm/ipic.h>
13
14#define NR_IPIC_INTS 128
15
16/* External IRQS */
17#define IPIC_IRQ_EXT0 48
18#define IPIC_IRQ_EXT1 17
19#define IPIC_IRQ_EXT7 23
20
21/* Default Priority Registers */
22#define IPIC_PRIORITY_DEFAULT 0x05309770
23
24/* System Global Interrupt Configuration Register */
25#define SICFR_IPSA 0x00010000
26#define SICFR_IPSB 0x00020000
27#define SICFR_IPSC 0x00040000
28#define SICFR_IPSD 0x00080000
29#define SICFR_MPSA 0x00200000
30#define SICFR_MPSB 0x00400000
31
32/* System External Interrupt Mask Register */
33#define SEMSR_SIRQ0 0x00008000
34
35/* System Error Control Register */
36#define SERCR_MCPR 0x00000001
37
38struct ipic {
39 volatile u32 __iomem *regs;
40
41 /* The remapper for this IPIC */
42 struct irq_domain *irqhost;
43};
44
45struct ipic_info {
46 u8 ack; /* pending register offset from base if the irq
47 supports ack operation */
48 u8 mask; /* mask register offset from base */
49 u8 prio; /* priority register offset from base */
50 u8 force; /* force register offset from base */
51 u8 bit; /* register bit position (as per doc)
52 bit mask = 1 << (31 - bit) */
53 u8 prio_mask; /* priority mask value */
54};
55
56#endif /* __IPIC_H__ */