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| 2 | |
| 3 | * Copyright (C) 2017 Linaro Ltd. <[email protected]>
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| 4 | * Copyright (C) 2023 SiFive
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| 5 |
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| 6 |
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| 7 | #ifndef __ASM_SIMD_H
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| 8 | #define __ASM_SIMD_H
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| 9 |
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| 10 | #include <linux/compiler.h>
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| 11 | #include <linux/irqflags.h>
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| 12 | #include <linux/percpu.h>
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| 13 | #include <linux/preempt.h>
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| 14 | #include <linux/types.h>
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| 15 | #include <linux/thread_info.h>
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| 16 |
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| 17 | #include <asm/vector.h>
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| 18 |
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| 19 | #ifdef CONFIG_RISCV_ISA_V
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| 20 | |
| 21 | * may_use_simd - whether it is allowable at this time to issue vector
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| 22 | * instructions or access the vector register file
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| 23 | *
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| 24 | * Callers must not assume that the result remains true beyond the next
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| 25 | * preempt_enable() or return from softirq context.
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| 26 |
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| 27 | static __must_check inline bool may_use_simd(void)
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| 28 | {
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| 29 | |
| 30 | * RISCV_KERNEL_MODE_V is only set while preemption is disabled,
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| 31 | * and is clear whenever preemption is enabled.
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| 32 |
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| 33 | if (in_hardirq() || in_nmi())
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| 34 | return false;
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| 35 |
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| 36 | |
| 37 | * Nesting is achieved in preempt_v by spreading the control for
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| 38 | * preemptible and non-preemptible kernel-mode Vector into two fields.
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| 39 | * Only non-preempt_v can nest on top of preempt_v, if non-preempt_v is
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| 40 | * unavailable, then preempt_v is not allowed.
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| 41 |
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| 42 | return !(riscv_v_flags() & RISCV_KERNEL_MODE_V);
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| 43 | }
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| 44 |
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| 45 | #else
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| 46 |
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| 47 | static __must_check inline bool may_use_simd(void)
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| 48 | {
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| 49 | return false;
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| 50 | }
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| 51 |
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| 52 | #endif
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| 53 |
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| 54 | #endif
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