| 1 | |
| 2 | *
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| 3 | * Copyright (C) 1999 by Kaz Kojima
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| 4 | *
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| 5 | * Defitions for the address spaces of the SH CPUs.
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| 6 |
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| 7 | #ifndef __ASM_SH_ADDRSPACE_H
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| 8 | #define __ASM_SH_ADDRSPACE_H
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| 9 |
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| 10 | #include <cpu/addrspace.h>
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| 11 |
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| 12 |
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| 13 | #ifdef P1SEG
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| 14 |
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| 15 | |
| 16 | [ P0/U0 (virtual) ] 0x00000000 <------ User space
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| 17 | [ P1 (fixed) cached ] 0x80000000 <------ Kernel space
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| 18 | [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access
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| 19 | [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area
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| 20 | [ P4 control ] 0xE0000000
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| 21 |
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| 22 |
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| 23 |
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| 24 | #define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
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| 25 |
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| 26 | #ifdef CONFIG_29BIT
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| 27 | |
| 28 | * Map an address to a certain privileged segment
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| 29 |
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| 30 | #define P1SEGADDR(a) \
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| 31 | ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
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| 32 | #define P2SEGADDR(a) \
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| 33 | ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
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| 34 | #define P3SEGADDR(a) \
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| 35 | ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
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| 36 | #define P4SEGADDR(a) \
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| 37 | ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
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| 38 | #else
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| 39 | |
| 40 | * These will never work in 32-bit, don't even bother.
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| 41 |
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| 42 | #define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; })
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| 43 | #define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; })
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| 44 | #define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; })
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| 45 | #define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; })
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| 46 | #endif
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| 47 | #endif
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| 48 |
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| 49 |
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| 50 | #define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000)
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| 51 |
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| 52 | #ifdef CONFIG_SH_STORE_QUEUES
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| 53 | |
| 54 | * This is a special case for the SH-4 store queues, as pages for this
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| 55 | * space still need to be faulted in before it's possible to flush the
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| 56 | * store queue cache for writeout to the remapped region.
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| 57 |
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| 58 | #define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000)
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| 59 | #else
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| 60 | #define P3_ADDR_MAX P4SEG
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| 61 | #endif
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| 62 |
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| 63 | #endif
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