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1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * This file contains the functions and defines necessary to modify and
4 * use the SuperH page table tree.
5 *
6 * Copyright (C) 1999 Niibe Yutaka
7 * Copyright (C) 2002 - 2007 Paul Mundt
8 */
9#ifndef __ASM_SH_PGTABLE_H
10#define __ASM_SH_PGTABLE_H
11
12#ifdef CONFIG_X2TLB
13#include <asm/pgtable-3level.h>
14#else
15#include <asm/pgtable-2level.h>
16#endif
17#include <asm/page.h>
18#include <asm/mmu.h>
19
20#ifndef __ASSEMBLER__
21#include <asm/addrspace.h>
22#include <asm/fixmap.h>
23#endif /* !__ASSEMBLER__ */
24
25/*
26 * Effective and physical address definitions, to aid with sign
27 * extension.
28 */
29#define NEFF 32
30#define NEFF_SIGN (1LL << (NEFF - 1))
31#define NEFF_MASK (-1LL << NEFF)
32
33static inline unsigned long long neff_sign_extend(unsigned long val)
34{
35 unsigned long long extended = val;
36 return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
37}
38
39#ifdef CONFIG_29BIT
40#define NPHYS 29
41#else
42#define NPHYS 32
43#endif
44
45#define NPHYS_SIGN (1LL << (NPHYS - 1))
46#define NPHYS_MASK (-1LL << NPHYS)
47
48#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
49#define PGDIR_MASK (~(PGDIR_SIZE-1))
50
51/* Entries per level */
52#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
53
54#define PHYS_ADDR_MASK29 0x1fffffff
55#define PHYS_ADDR_MASK32 0xffffffff
56
57static inline unsigned long phys_addr_mask(void)
58{
59 /* Is the MMU in 29bit mode? */
60 if (__in_29bit_mode())
61 return PHYS_ADDR_MASK29;
62
63 return PHYS_ADDR_MASK32;
64}
65
66#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
67#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
68
69#define VMALLOC_START (P3SEG)
70#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
71
72#include <asm/pgtable_32.h>
73
74/*
75 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
76 * protection for execute, and considers it the same as a read. Also, write
77 * permission implies read permission. This is the closest we can get..
78 *
79 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
80 * not only supporting separate execute, read, and write bits, but having
81 * completely separate permission bits for user and kernel space.
82 */
83 /*xwr*/
84
85typedef pte_t *pte_addr_t;
86
87#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
88
89struct vm_area_struct;
90struct mm_struct;
91
92extern void __update_cache(struct vm_area_struct *vma,
93 unsigned long address, pte_t pte);
94extern void __update_tlb(struct vm_area_struct *vma,
95 unsigned long address, pte_t pte);
96
97static inline void update_mmu_cache_range(struct vm_fault *vmf,
98 struct vm_area_struct *vma, unsigned long address,
99 pte_t *ptep, unsigned int nr)
100{
101 pte_t pte = *ptep;
102 __update_cache(vma, address, pte);
103 __update_tlb(vma, address, pte);
104}
105#define update_mmu_cache(vma, addr, ptep) \
106 update_mmu_cache_range(NULL, vma, addr, ptep, 1)
107
108extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
109extern void paging_init(void);
110extern void page_table_range_init(unsigned long start, unsigned long end,
111 pgd_t *pgd);
112
113static inline bool __pte_access_permitted(pte_t pte, u64 prot)
114{
115 return (pte_val(pte) & (prot | _PAGE_SPECIAL)) == prot;
116}
117
118#ifdef CONFIG_X2TLB
119static inline bool pte_access_permitted(pte_t pte, bool write)
120{
121 u64 prot = _PAGE_PRESENT;
122
123 prot |= _PAGE_EXT(_PAGE_EXT_KERN_READ | _PAGE_EXT_USER_READ);
124 if (write)
125 prot |= _PAGE_EXT(_PAGE_EXT_KERN_WRITE | _PAGE_EXT_USER_WRITE);
126 return __pte_access_permitted(pte, prot);
127}
128#else
129static inline bool pte_access_permitted(pte_t pte, bool write)
130{
131 u64 prot = _PAGE_PRESENT | _PAGE_USER;
132
133 if (write)
134 prot |= _PAGE_RW;
135 return __pte_access_permitted(pte, prot);
136}
137#endif
138
139#define pte_access_permitted pte_access_permitted
140
141/* arch/sh/mm/mmap.c */
142#define HAVE_ARCH_UNMAPPED_AREA
143#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
144
145#endif /* __ASM_SH_PGTABLE_H */