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1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * include/asm-sh/cpu-sh3/cache.h
4 *
5 * Copyright (C) 1999 Niibe Yutaka
6 */
7#ifndef __ASM_CPU_SH3_CACHE_H
8#define __ASM_CPU_SH3_CACHE_H
9
10#define L1_CACHE_SHIFT 4
11
12#define SH_CACHE_VALID 1
13#define SH_CACHE_UPDATED 2
14#define SH_CACHE_COMBINED 4
15#define SH_CACHE_ASSOC 8
16
17#define SH_CCR 0xffffffec /* Address of Cache Control Register */
18
19#define CCR_CACHE_CE 0x01 /* Cache Enable */
20#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
21#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
22#define CCR_CACHE_CF 0x08 /* Cache Flush */
23#define CCR_CACHE_ORA 0x20 /* RAM mode */
24
25#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
26#define CACHE_PHYSADDR_MASK 0x1ffffc00
27
28#define CCR_CACHE_ENABLE CCR_CACHE_CE
29#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
30
31#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7721)
35#define CCR3_REG 0xa40000b4
36#define CCR_CACHE_16KB 0x00010000
37#define CCR_CACHE_32KB 0x00020000
38#endif
39
40#endif /* __ASM_CPU_SH3_CACHE_H */