| 1 | |
| 2 | |
| 3 | * arch/sh/kernel/cpu/sh2a/opcode_helper.c
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| 4 | *
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| 5 | * Helper for the SH-2A 32-bit opcodes.
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| 6 | *
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| 7 | * Copyright (C) 2007 Paul Mundt
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| 8 |
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| 9 | #include <linux/kernel.h>
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| 10 |
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| 11 | #include <asm/processor.h>
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| 12 |
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| 13 | |
| 14 | * Instructions on SH are generally fixed at 16-bits, however, SH-2A
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| 15 | * introduces some 32-bit instructions. Since there are no real
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| 16 | * constraints on their use (and they can be mixed and matched), we need
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| 17 | * to check the instruction encoding to work out if it's a true 32-bit
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| 18 | * instruction or not.
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| 19 | *
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| 20 | * Presently, 32-bit opcodes have only slight variations in what the
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| 21 | * actual encoding looks like in the first-half of the instruction, which
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| 22 | * makes it fairly straightforward to differentiate from the 16-bit ones.
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| 23 | *
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| 24 | * First 16-bits of encoding Used by
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| 25 | *
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| 26 | * 0011nnnnmmmm0001 mov.b, mov.w, mov.l, fmov.d,
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| 27 | * fmov.s, movu.b, movu.w
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| 28 | *
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| 29 | * 0011nnnn0iii1001 bclr.b, bld.b, bset.b, bst.b, band.b,
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| 30 | * bandnot.b, bldnot.b, bor.b, bornot.b,
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| 31 | * bxor.b
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| 32 | *
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| 33 | * 0000nnnniiii0000 movi20
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| 34 | * 0000nnnniiii0001 movi20s
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| 35 |
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| 36 | unsigned int instruction_size(unsigned int insn)
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| 37 | {
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| 38 |
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| 39 | switch ((insn & 0xf00f)) {
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| 40 | case 0x0000:
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| 41 | case 0x0001:
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| 42 | case 0x3001:
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| 43 | return 4;
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| 44 | }
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| 45 |
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| 46 |
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| 47 | switch ((insn & 0xf08f)) {
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| 48 | case 0x3009:
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| 49 | return 4;
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| 50 | }
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| 51 |
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| 52 | return 2;
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| 53 | }
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