| 1 | /* SPDX-License-Identifier: GPL-2.0 */
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| 2 | /*
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| 3 | * rtrap.S: Preparing for return from trap on Sparc V9.
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| 4 | *
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| 5 | * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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| 6 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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| 7 | */
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| 8 |
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| 9 |
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| 10 | |
| 11 | |
| 12 | |
| 13 | |
| 14 | |
| 15 | |
| 16 | |
| 17 |
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| 18 | |
| 19 | |
| 20 | |
| 21 | |
| 22 | |
| 23 |
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| 24 | .text
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| 25 | .align 32
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| 26 | __handle_preemption:
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| 27 | call SCHEDULE_USER
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| 28 | 661: wrpr %g0, RTRAP_PSTATE, %pstate
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| 29 | /* If userspace is using ADI, it could potentially pass
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| 30 | * a pointer with version tag embedded in it. To maintain
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| 31 | * the ADI security, we must re-enable PSTATE.mcde before
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| 32 | * we continue execution in the kernel for another thread.
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| 33 | */
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| 34 | .section .sun_m7_1insn_patch, "ax"
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| 35 | .word 661b
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| 36 | wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
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| 37 | .previous
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| 38 | ba,pt %xcc, __handle_preemption_continue
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| 39 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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| 40 |
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| 41 | __handle_user_windows:
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| 42 | add %sp, PTREGS_OFF, %o0
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| 43 | call fault_in_user_windows
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| 44 | 661: wrpr %g0, RTRAP_PSTATE, %pstate
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| 45 | /* If userspace is using ADI, it could potentially pass
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| 46 | * a pointer with version tag embedded in it. To maintain
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| 47 | * the ADI security, we must re-enable PSTATE.mcde before
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| 48 | * we continue execution in the kernel for another thread.
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| 49 | */
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| 50 | .section .sun_m7_1insn_patch, "ax"
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| 51 | .word 661b
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| 52 | wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
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| 53 | .previous
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| 54 | ba,pt %xcc, __handle_preemption_continue
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| 55 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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| 56 |
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| 57 | __handle_userfpu:
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| 58 | rd %fprs, %l5
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| 59 | andcc %l5, FPRS_FEF, %g0
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| 60 | sethi %hi(TSTATE_PEF), %o0
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| 61 | be,a,pn %icc, __handle_userfpu_continue
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| 62 | andn %l1, %o0, %l1
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| 63 | ba,a,pt %xcc, __handle_userfpu_continue
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| 64 |
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| 65 | __handle_signal:
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| 66 | mov %l5, %o1
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| 67 | add %sp, PTREGS_OFF, %o0
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| 68 | mov %l0, %o2
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| 69 | call do_notify_resume
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| 70 | 661: wrpr %g0, RTRAP_PSTATE, %pstate
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| 71 | /* If userspace is using ADI, it could potentially pass
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| 72 | * a pointer with version tag embedded in it. To maintain
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| 73 | * the ADI security, we must re-enable PSTATE.mcde before
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| 74 | * we continue execution in the kernel for another thread.
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| 75 | */
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| 76 | .section .sun_m7_1insn_patch, "ax"
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| 77 | .word 661b
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| 78 | wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
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| 79 | .previous
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| 80 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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| 81 |
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| 82 | /* Signal delivery can modify pt_regs tstate, so we must
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| 83 | * reload it.
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| 84 | */
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| 85 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
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| 86 | sethi %hi(0xf << 20), %l4
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| 87 | and %l1, %l4, %l4
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| 88 | andn %l1, %l4, %l1
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| 89 | ba,pt %xcc, __handle_preemption_continue
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| 90 | srl %l4, 20, %l4
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| 91 |
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| 92 | /* When returning from a NMI (%pil==15) interrupt we want to
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| 93 | * avoid running softirqs, doing IRQ tracing, preempting, etc.
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| 94 | */
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| 95 | .globl rtrap_nmi
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| 96 | rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
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| 97 | sethi %hi(0xf << 20), %l4
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| 98 | and %l1, %l4, %l4
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| 99 | andn %l1, %l4, %l1
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| 100 | srl %l4, 20, %l4
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| 101 | ba,pt %xcc, rtrap_no_irq_enable
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| 102 | nop
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| 103 | /* Do not actually set the %pil here. We will do that
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| 104 | * below after we clear PSTATE_IE in the %pstate register.
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| 105 | * If we re-enable interrupts here, we can recurse down
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| 106 | * the hardirq stack potentially endlessly, causing a
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| 107 | * stack overflow.
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| 108 | */
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| 109 |
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| 110 | .align 64
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| 111 | .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
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| 112 | rtrap_irq:
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| 113 | rtrap:
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| 114 | /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
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| 115 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
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| 116 | rtrap_xcall:
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| 117 | sethi %hi(0xf << 20), %l4
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| 118 | and %l1, %l4, %l4
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| 119 | andn %l1, %l4, %l1
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| 120 | srl %l4, 20, %l4
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| 121 | |
| 122 | brnz,pn %l4, rtrap_no_irq_enable
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| 123 | nop
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| 124 | call trace_hardirqs_on
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| 125 | nop
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| 126 | /* Do not actually set the %pil here. We will do that
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| 127 | * below after we clear PSTATE_IE in the %pstate register.
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| 128 | * If we re-enable interrupts here, we can recurse down
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| 129 | * the hardirq stack potentially endlessly, causing a
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| 130 | * stack overflow.
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| 131 | *
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| 132 | * It is tempting to put this test and trace_hardirqs_on
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| 133 | * call at the 'rt_continue' label, but that will not work
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| 134 | * as that path hits unconditionally and we do not want to
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| 135 | * execute this in NMI return paths, for example.
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| 136 | */
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| 137 | |
| 138 | rtrap_no_irq_enable:
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| 139 | andcc %l1, TSTATE_PRIV, %l3
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| 140 | bne,pn %icc, to_kernel
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| 141 | nop
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| 142 |
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| 143 | /* We must hold IRQs off and atomically test schedule+signal
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| 144 | * state, then hold them off all the way back to userspace.
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| 145 | * If we are returning to kernel, none of this matters. Note
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| 146 | * that we are disabling interrupts via PSTATE_IE, not using
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| 147 | * %pil.
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| 148 | *
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| 149 | * If we do not do this, there is a window where we would do
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| 150 | * the tests, later the signal/resched event arrives but we do
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| 151 | * not process it since we are still in kernel mode. It would
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| 152 | * take until the next local IRQ before the signal/resched
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| 153 | * event would be handled.
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| 154 | *
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| 155 | * This also means that if we have to deal with user
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| 156 | * windows, we have to redo all of these sched+signal checks
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| 157 | * with IRQs disabled.
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| 158 | */
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| 159 | to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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| 160 | wrpr 0, %pil
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| 161 | __handle_preemption_continue:
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| 162 | ldx [%g6 + TI_FLAGS], %l0
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| 163 | sethi %hi(_TIF_USER_WORK_MASK), %o0
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| 164 | or %o0, %lo(_TIF_USER_WORK_MASK), %o0
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| 165 | andcc %l0, %o0, %g0
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| 166 | sethi %hi(TSTATE_PEF), %o0
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| 167 | be,pt %xcc, user_nowork
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| 168 | andcc %l1, %o0, %g0
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| 169 | andcc %l0, _TIF_NEED_RESCHED, %g0
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| 170 | bne,pn %xcc, __handle_preemption
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| 171 | andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
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| 172 | bne,pn %xcc, __handle_signal
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| 173 | ldub [%g6 + TI_WSAVED], %o2
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| 174 | brnz,pn %o2, __handle_user_windows
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| 175 | nop
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| 176 | sethi %hi(TSTATE_PEF), %o0
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| 177 | andcc %l1, %o0, %g0
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| 178 |
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| 179 | /* This fpdepth clear is necessary for non-syscall rtraps only */
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| 180 | user_nowork:
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| 181 | bne,pn %xcc, __handle_userfpu
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| 182 | stb %g0, [%g6 + TI_FPDEPTH]
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| 183 | __handle_userfpu_continue:
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| 184 |
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| 185 | rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
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| 186 | ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
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| 187 |
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| 188 | ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
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| 189 | ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
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| 190 | ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
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| 191 | brz,pt %l3, 1f
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| 192 | mov %g6, %l2
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| 193 |
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| 194 | /* Must do this before thread reg is clobbered below. */
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| 195 | LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
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| 196 | 1:
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| 197 | ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
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| 198 | ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
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| 199 |
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| 200 | /* Normal globals are restored, go to trap globals. */
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| 201 | 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
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| 202 | nop
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| 203 | .section .sun4v_2insn_patch, "ax"
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| 204 | .word 661b
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| 205 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
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| 206 | SET_GL(1)
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| 207 | .previous
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| 208 |
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| 209 | mov %l2, %g6
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| 210 |
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| 211 | ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
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| 212 | ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
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| 213 |
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| 214 | ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
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| 215 | ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
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| 216 | ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
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| 217 | ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
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| 218 | ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
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| 219 | ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
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| 220 | ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
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| 221 | ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
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| 222 |
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| 223 | ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
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| 224 | wr %o3, %g0, %y
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| 225 | wrpr %l4, 0x0, %pil
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| 226 | wrpr %g0, 0x1, %tl
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| 227 | andn %l1, TSTATE_SYSCALL, %l1
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| 228 | wrpr %l1, %g0, %tstate
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| 229 | wrpr %l2, %g0, %tpc
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| 230 | wrpr %o2, %g0, %tnpc
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| 231 |
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| 232 | brnz,pn %l3, kern_rtt
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| 233 | mov PRIMARY_CONTEXT, %l7
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| 234 |
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| 235 | 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
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| 236 | .section .sun4v_1insn_patch, "ax"
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| 237 | .word 661b
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| 238 | ldxa [%l7 + %l7] ASI_MMU, %l0
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| 239 | .previous
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| 240 |
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| 241 | sethi %hi(sparc64_kern_pri_nuc_bits), %l1
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| 242 | ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
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| 243 | or %l0, %l1, %l0
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| 244 |
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| 245 | 661: stxa %l0, [%l7] ASI_DMMU
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| 246 | .section .sun4v_1insn_patch, "ax"
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| 247 | .word 661b
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| 248 | stxa %l0, [%l7] ASI_MMU
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| 249 | .previous
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| 250 |
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| 251 | sethi %hi(KERNBASE), %l7
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| 252 | flush %l7
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| 253 | rdpr %wstate, %l1
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| 254 | rdpr %otherwin, %l2
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| 255 | srl %l1, 3, %l1
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| 256 |
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| 257 | 661: wrpr %l2, %g0, %canrestore
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| 258 | .section .fast_win_ctrl_1insn_patch, "ax"
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| 259 | .word 661b
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| 260 | .word 0x89880000 ! normalw
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| 261 | .previous
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| 262 |
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| 263 | wrpr %l1, %g0, %wstate
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| 264 | brnz,pt %l2, user_rtt_restore
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| 265 | 661: wrpr %g0, %g0, %otherwin
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| 266 | .section .fast_win_ctrl_1insn_patch, "ax"
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| 267 | .word 661b
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| 268 | nop
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| 269 | .previous
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| 270 |
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| 271 | ldx [%g6 + TI_FLAGS], %g3
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| 272 | wr %g0, ASI_AIUP, %asi
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| 273 | rdpr %cwp, %g1
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| 274 | andcc %g3, _TIF_32BIT, %g0
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| 275 | sub %g1, 1, %g1
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| 276 | bne,pt %xcc, user_rtt_fill_32bit
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| 277 | wrpr %g1, %cwp
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| 278 | ba,a,pt %xcc, user_rtt_fill_64bit
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| 279 | nop
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| 280 |
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| 281 | user_rtt_fill_fixup_dax:
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| 282 | ba,pt %xcc, user_rtt_fill_fixup_common
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| 283 | mov 1, %g3
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| 284 |
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| 285 | user_rtt_fill_fixup_mna:
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| 286 | ba,pt %xcc, user_rtt_fill_fixup_common
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| 287 | mov 2, %g3
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| 288 |
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| 289 | user_rtt_fill_fixup:
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| 290 | ba,pt %xcc, user_rtt_fill_fixup_common
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| 291 | clr %g3
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| 292 |
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| 293 | user_rtt_pre_restore:
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| 294 | add %g1, 1, %g1
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| 295 | wrpr %g1, 0x0, %cwp
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| 296 |
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| 297 | user_rtt_restore:
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| 298 | restore
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| 299 | rdpr %canrestore, %g1
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| 300 | wrpr %g1, 0x0, %cleanwin
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| 301 | retry
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| 302 | nop
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| 303 |
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| 304 | kern_rtt: rdpr %canrestore, %g1
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| 305 | brz,pn %g1, kern_rtt_fill
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| 306 | nop
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| 307 | kern_rtt_restore:
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| 308 | stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
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| 309 | restore
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| 310 | retry
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| 311 |
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| 312 | to_kernel:
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| 313 | |
| 314 | ldsw [%g6 + TI_PRE_COUNT], %l5
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| 315 | brnz %l5, kern_fpucheck
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| 316 | ldx [%g6 + TI_FLAGS], %l5
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| 317 | andcc %l5, _TIF_NEED_RESCHED, %g0
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| 318 | be,pt %xcc, kern_fpucheck
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| 319 | nop
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| 320 | cmp %l4, 0
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| 321 | bne,pn %xcc, kern_fpucheck
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| 322 | nop
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| 323 | call preempt_schedule_irq
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| 324 | nop
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| 325 | ba,pt %xcc, rtrap
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| 326 | |
| 327 | kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
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| 328 | brz,pt %l5, rt_continue
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| 329 | srl %l5, 1, %o0
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| 330 | add %g6, TI_FPSAVED, %l6
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| 331 | ldub [%l6 + %o0], %l2
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| 332 | sub %l5, 2, %l5
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| 333 |
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| 334 | add %g6, TI_GSR, %o1
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| 335 | andcc %l2, (FPRS_FEF|FPRS_DU), %g0
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| 336 | be,pt %icc, 2f
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| 337 | and %l2, FPRS_DL, %l6
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| 338 | andcc %l2, FPRS_FEF, %g0
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| 339 | be,pn %icc, 5f
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| 340 | sll %o0, 3, %o5
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| 341 | rd %fprs, %g1
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| 342 |
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| 343 | wr %g1, FPRS_FEF, %fprs
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| 344 | ldx [%o1 + %o5], %g1
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| 345 | add %g6, TI_XFSR, %o1
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| 346 | sll %o0, 8, %o2
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| 347 | add %g6, TI_FPREGS, %o3
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| 348 | brz,pn %l6, 1f
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| 349 | add %g6, TI_FPREGS+0x40, %o4
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| 350 |
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| 351 | membar |
| 352 | ldda [%o3 + %o2] ASI_BLK_P, %f0
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| 353 | ldda [%o4 + %o2] ASI_BLK_P, %f16
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| 354 | membar |
| 355 | 1: andcc %l2, FPRS_DU, %g0
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| 356 | be,pn %icc, 1f
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| 357 | wr %g1, 0, %gsr
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| 358 | add %o2, 0x80, %o2
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| 359 | membar |
| 360 | ldda [%o3 + %o2] ASI_BLK_P, %f32
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| 361 | ldda [%o4 + %o2] ASI_BLK_P, %f48
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| 362 | 1: membar |
| 363 | ldx [%o1 + %o5], %fsr
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| 364 | 2: stb %l5, [%g6 + TI_FPDEPTH]
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| 365 | ba,pt %xcc, rt_continue
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| 366 | nop
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| 367 | 5: wr %g0, FPRS_FEF, %fprs
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| 368 | sll %o0, 8, %o2
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| 369 |
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| 370 | add %g6, TI_FPREGS+0x80, %o3
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| 371 | add %g6, TI_FPREGS+0xc0, %o4
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| 372 | membar |
| 373 | ldda [%o3 + %o2] ASI_BLK_P, %f32
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| 374 | ldda [%o4 + %o2] ASI_BLK_P, %f48
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| 375 | membar |
| 376 | wr %g0, FPRS_DU, %fprs
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| 377 | ba,pt %xcc, rt_continue
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| 378 | stb %l5, [%g6 + TI_FPDEPTH]
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