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1// SPDX-License-Identifier: GPL-2.0
2/* linux/arch/sparc/kernel/time.c
3 *
4 * Copyright (C) 1995 David S. Miller ([email protected])
5 * Copyright (C) 1996 Thomas K. Dyas ([email protected])
6 *
7 * Chris Davis ([email protected]) 03/27/1998
8 * Added support for the intersil on the sun4/4200
9 *
10 * Gleb Raiko ([email protected]) 08/18/1998
11 * Support for MicroSPARC-IIep, PCI CPU.
12 *
13 * This file handles the Sparc specific time handling details.
14 *
15 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
16 * "A Kernel Model for Precision Timekeeping" by Dave Mills
17 */
18#include <linux/errno.h>
19#include <linux/module.h>
20#include <linux/sched.h>
21#include <linux/kernel.h>
22#include <linux/param.h>
23#include <linux/string.h>
24#include <linux/mm.h>
25#include <linux/interrupt.h>
26#include <linux/time.h>
27#include <linux/rtc/m48t59.h>
28#include <linux/timex.h>
29#include <linux/clocksource.h>
30#include <linux/clockchips.h>
31#include <linux/init.h>
32#include <linux/pci.h>
33#include <linux/ioport.h>
34#include <linux/profile.h>
35#include <linux/of.h>
36#include <linux/platform_device.h>
37
38#include <asm/mc146818rtc.h>
39#include <asm/oplib.h>
40#include <asm/timex.h>
41#include <asm/timer.h>
42#include <asm/irq.h>
43#include <asm/io.h>
44#include <asm/idprom.h>
45#include <asm/page.h>
46#include <asm/pcic.h>
47#include <asm/irq_regs.h>
48#include <asm/setup.h>
49
50#include "kernel.h"
51#include "irq.h"
52
53static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
54static __volatile__ u64 timer_cs_internal_counter = 0;
55static char timer_cs_enabled = 0;
56
57static struct clock_event_device timer_ce;
58static char timer_ce_enabled = 0;
59
60#ifdef CONFIG_SMP
61DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
62#endif
63
64DEFINE_SPINLOCK(rtc_lock);
65EXPORT_SYMBOL(rtc_lock);
66
67unsigned long profile_pc(struct pt_regs *regs)
68{
69 extern char __copy_user_begin[], __copy_user_end[];
70 extern char __bzero_begin[], __bzero_end[];
71
72 unsigned long pc = regs->pc;
73
74 if (in_lock_functions(pc) ||
75 (pc >= (unsigned long) __copy_user_begin &&
76 pc < (unsigned long) __copy_user_end) ||
77 (pc >= (unsigned long) __bzero_begin &&
78 pc < (unsigned long) __bzero_end))
79 pc = regs->u_regs[UREG_RETPC];
80 return pc;
81}
82
83EXPORT_SYMBOL(profile_pc);
84
85volatile u32 __iomem *master_l10_counter;
86
87irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
88{
89 if (timer_cs_enabled) {
90 write_seqlock(&timer_cs_lock);
91 timer_cs_internal_counter++;
92 sparc_config.clear_clock_irq();
93 write_sequnlock(&timer_cs_lock);
94 } else {
95 sparc_config.clear_clock_irq();
96 }
97
98 if (timer_ce_enabled)
99 timer_ce.event_handler(&timer_ce);
100
101 return IRQ_HANDLED;
102}
103
104static int timer_ce_shutdown(struct clock_event_device *evt)
105{
106 timer_ce_enabled = 0;
107 smp_mb();
108 return 0;
109}
110
111static int timer_ce_set_periodic(struct clock_event_device *evt)
112{
113 timer_ce_enabled = 1;
114 smp_mb();
115 return 0;
116}
117
118static __init void setup_timer_ce(void)
119{
120 struct clock_event_device *ce = &timer_ce;
121
122 BUG_ON(smp_processor_id() != boot_cpu_id);
123
124 ce->name = "timer_ce";
125 ce->rating = 100;
126 ce->features = CLOCK_EVT_FEAT_PERIODIC;
127 ce->set_state_shutdown = timer_ce_shutdown;
128 ce->set_state_periodic = timer_ce_set_periodic;
129 ce->tick_resume = timer_ce_set_periodic;
130 ce->cpumask = cpu_possible_mask;
131 ce->shift = 32;
132 ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
133 ce->shift);
134 clockevents_register_device(ce);
135}
136
137static unsigned int sbus_cycles_offset(void)
138{
139 u32 val, offset;
140
141 val = sbus_readl(master_l10_counter);
142 offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
143
144 /* Limit hit? */
145 if (val & TIMER_LIMIT_BIT)
146 offset += sparc_config.cs_period;
147
148 return offset;
149}
150
151static u64 timer_cs_read(struct clocksource *cs)
152{
153 unsigned int seq, offset;
154 u64 cycles;
155
156 do {
157 seq = read_seqbegin(&timer_cs_lock);
158
159 cycles = timer_cs_internal_counter;
160 offset = sparc_config.get_cycles_offset();
161 } while (read_seqretry(&timer_cs_lock, seq));
162
163 /* Count absolute cycles */
164 cycles *= sparc_config.cs_period;
165 cycles += offset;
166
167 return cycles;
168}
169
170static struct clocksource timer_cs = {
171 .name = "timer_cs",
172 .rating = 100,
173 .read = timer_cs_read,
174 .mask = CLOCKSOURCE_MASK(64),
175 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
176};
177
178static __init int setup_timer_cs(void)
179{
180 timer_cs_enabled = 1;
181 return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
182}
183
184#ifdef CONFIG_SMP
185static int percpu_ce_shutdown(struct clock_event_device *evt)
186{
187 int cpu = cpumask_first(evt->cpumask);
188
189 sparc_config.load_profile_irq(cpu, 0);
190 return 0;
191}
192
193static int percpu_ce_set_periodic(struct clock_event_device *evt)
194{
195 int cpu = cpumask_first(evt->cpumask);
196
197 sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
198 return 0;
199}
200
201static int percpu_ce_set_next_event(unsigned long delta,
202 struct clock_event_device *evt)
203{
204 int cpu = cpumask_first(evt->cpumask);
205 unsigned int next = (unsigned int)delta;
206
207 sparc_config.load_profile_irq(cpu, next);
208 return 0;
209}
210
211void register_percpu_ce(int cpu)
212{
213 struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
214 unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
215
216 if (sparc_config.features & FEAT_L14_ONESHOT)
217 features |= CLOCK_EVT_FEAT_ONESHOT;
218
219 ce->name = "percpu_ce";
220 ce->rating = 200;
221 ce->features = features;
222 ce->set_state_shutdown = percpu_ce_shutdown;
223 ce->set_state_periodic = percpu_ce_set_periodic;
224 ce->set_state_oneshot = percpu_ce_shutdown;
225 ce->set_next_event = percpu_ce_set_next_event;
226 ce->cpumask = cpumask_of(cpu);
227 ce->shift = 32;
228 ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
229 ce->shift);
230 ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
231 ce->max_delta_ticks = (unsigned long)sparc_config.clock_rate;
232 ce->min_delta_ns = clockevent_delta2ns(100, ce);
233 ce->min_delta_ticks = 100;
234
235 clockevents_register_device(ce);
236}
237#endif
238
239static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
240{
241 struct platform_device *pdev = to_platform_device(dev);
242 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
243
244 return readb(pdata->ioaddr + ofs);
245}
246
247static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
248{
249 struct platform_device *pdev = to_platform_device(dev);
250 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
251
252 writeb(val, pdata->ioaddr + ofs);
253}
254
255static struct m48t59_plat_data m48t59_data = {
256 .read_byte = mostek_read_byte,
257 .write_byte = mostek_write_byte,
258 .yy_offset = 68,
259};
260
261/* resource is set at runtime */
262static struct platform_device m48t59_rtc = {
263 .name = "rtc-m48t59",
264 .id = 0,
265 .num_resources = 1,
266 .dev = {
267 .platform_data = &m48t59_data,
268 },
269};
270
271static int clock_probe(struct platform_device *op)
272{
273 struct device_node *dp = op->dev.of_node;
274 const char *model = of_get_property(dp, "model", NULL);
275
276 if (!model)
277 return -ENODEV;
278
279 /* Only the primary RTC has an address property */
280 if (!of_property_present(dp, "address"))
281 return -ENODEV;
282
283 m48t59_rtc.resource = &op->resource[0];
284 if (!strcmp(model, "mk48t02")) {
285 /* Map the clock register io area read-only */
286 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
287 2048, "rtc-m48t59");
288 m48t59_data.type = M48T59RTC_TYPE_M48T02;
289 } else if (!strcmp(model, "mk48t08")) {
290 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
291 8192, "rtc-m48t59");
292 m48t59_data.type = M48T59RTC_TYPE_M48T08;
293 } else
294 return -ENODEV;
295
296 if (platform_device_register(&m48t59_rtc) < 0)
297 printk(KERN_ERR "Registering RTC device failed\n");
298
299 return 0;
300}
301
302static const struct of_device_id clock_match[] = {
303 {
304 .name = "eeprom",
305 },
306 {},
307};
308
309static struct platform_driver clock_driver = {
310 .probe = clock_probe,
311 .driver = {
312 .name = "rtc",
313 .of_match_table = clock_match,
314 },
315};
316
317
318/* Probe for the mostek real time clock chip. */
319static int __init clock_init(void)
320{
321 return platform_driver_register(&clock_driver);
322}
323/* Must be after subsys_initcall() so that busses are probed. Must
324 * be before device_initcall() because things like the RTC driver
325 * need to see the clock registers.
326 */
327fs_initcall(clock_init);
328
329static void __init sparc32_late_time_init(void)
330{
331 if (sparc_config.features & FEAT_L10_CLOCKEVENT)
332 setup_timer_ce();
333 if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
334 setup_timer_cs();
335#ifdef CONFIG_SMP
336 register_percpu_ce(smp_processor_id());
337#endif
338}
339
340static void __init sbus_time_init(void)
341{
342 sparc_config.get_cycles_offset = sbus_cycles_offset;
343 sparc_config.init_timers();
344}
345
346void __init time_init(void)
347{
348 sparc_config.features = 0;
349 late_time_init = sparc32_late_time_init;
350
351 if (pcic_present())
352 pci_time_init();
353 else
354 sbus_time_init();
355}
356