| 1 |
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| 2 | #ifndef _ASM_X86_TEXT_PATCHING_H
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| 3 | #define _ASM_X86_TEXT_PATCHING_H
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| 4 |
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| 5 | #include <linux/types.h>
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| 6 | #include <linux/stddef.h>
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| 7 | #include <asm/ptrace.h>
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| 8 |
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| 9 | |
| 10 | * Currently, the max observed size in the kernel code is
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| 11 | * JUMP_LABEL_NOP_SIZE/RELATIVEJUMP_SIZE, which are 5.
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| 12 | * Raise it if needed.
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| 13 |
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| 14 | #define TEXT_POKE_MAX_OPCODE_SIZE 5
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| 15 |
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| 16 | extern void text_poke_early(void *addr, const void *opcode, size_t len);
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| 17 |
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| 18 | extern void text_poke_apply_relocation(u8 *buf, const u8 * const instr, size_t instrlen, u8 *repl, size_t repl_len);
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| 19 |
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| 20 | |
| 21 | * Clear and restore the kernel write-protection flag on the local CPU.
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| 22 | * Allows the kernel to edit read-only pages.
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| 23 | * Side-effect: any interrupt handler running between save and restore will have
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| 24 | * the ability to write to read-only pages.
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| 25 | *
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| 26 | * Warning:
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| 27 | * Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
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| 28 | * no thread can be preempted in the instructions being modified (no iret to an
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| 29 | * invalid instruction possible) or if the instructions are changed from a
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| 30 | * consistent state to another consistent state atomically.
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| 31 | * On the local CPU you need to be protected against NMI or MCE handlers seeing
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| 32 | * an inconsistent instruction while you patch.
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| 33 |
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| 34 | extern void *text_poke(void *addr, const void *opcode, size_t len);
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| 35 | extern void smp_text_poke_sync_each_cpu(void);
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| 36 | extern void *text_poke_kgdb(void *addr, const void *opcode, size_t len);
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| 37 | extern void *text_poke_copy(void *addr, const void *opcode, size_t len);
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| 38 | #define text_poke_copy text_poke_copy
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| 39 | extern void *text_poke_copy_locked(void *addr, const void *opcode, size_t len, bool core_ok);
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| 40 | extern void *text_poke_set(void *addr, int c, size_t len);
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| 41 | extern int smp_text_poke_int3_handler(struct pt_regs *regs);
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| 42 | extern void smp_text_poke_single(void *addr, const void *opcode, size_t len, const void *emulate);
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| 43 |
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| 44 | extern void smp_text_poke_batch_add(void *addr, const void *opcode, size_t len, const void *emulate);
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| 45 | extern void smp_text_poke_batch_finish(void);
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| 46 |
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| 47 | #define INT3_INSN_SIZE 1
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| 48 | #define INT3_INSN_OPCODE 0xCC
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| 49 |
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| 50 | #define RET_INSN_SIZE 1
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| 51 | #define RET_INSN_OPCODE 0xC3
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| 52 |
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| 53 | #define CALL_INSN_SIZE 5
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| 54 | #define CALL_INSN_OPCODE 0xE8
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| 55 |
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| 56 | #define JMP32_INSN_SIZE 5
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| 57 | #define JMP32_INSN_OPCODE 0xE9
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| 58 |
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| 59 | #define JMP8_INSN_SIZE 2
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| 60 | #define JMP8_INSN_OPCODE 0xEB
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| 61 |
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| 62 | #define DISP32_SIZE 4
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| 63 |
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| 64 | static __always_inline int text_opcode_size(u8 opcode)
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| 65 | {
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| 66 | int size = 0;
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| 67 |
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| 68 | #define __CASE(insn) \
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| 69 | case insn##_INSN_OPCODE: size = insn##_INSN_SIZE; break
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| 70 |
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| 71 | switch(opcode) {
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| 72 | __CASE(INT3);
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| 73 | __CASE(RET);
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| 74 | __CASE(CALL);
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| 75 | __CASE(JMP32);
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| 76 | __CASE(JMP8);
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| 77 | }
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| 78 |
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| 79 | #undef __CASE
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| 80 |
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| 81 | return size;
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| 82 | }
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| 83 |
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| 84 | union text_poke_insn {
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| 85 | u8 text[TEXT_POKE_MAX_OPCODE_SIZE];
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| 86 | struct {
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| 87 | u8 opcode;
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| 88 | s32 disp;
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| 89 | } __attribute__((packed));
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| 90 | };
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| 91 |
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| 92 | static __always_inline
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| 93 | void __text_gen_insn(void *buf, u8 opcode, const void *addr, const void *dest, int size)
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| 94 | {
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| 95 | union text_poke_insn *insn = buf;
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| 96 |
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| 97 | BUG_ON(size < text_opcode_size(opcode));
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| 98 |
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| 99 | |
| 100 | * Hide the addresses to avoid the compiler folding in constants when
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| 101 | * referencing code, these can mess up annotations like
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| 102 | * ANNOTATE_NOENDBR.
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| 103 |
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| 104 | OPTIMIZER_HIDE_VAR(insn);
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| 105 | OPTIMIZER_HIDE_VAR(addr);
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| 106 | OPTIMIZER_HIDE_VAR(dest);
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| 107 |
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| 108 | insn->opcode = opcode;
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| 109 |
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| 110 | if (size > 1) {
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| 111 | insn->disp = (long)dest - (long)(addr + size);
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| 112 | if (size == 2) {
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| 113 | |
| 114 | * Ensure that for JMP8 the displacement
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| 115 | * actually fits the signed byte.
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| 116 |
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| 117 | BUG_ON((insn->disp >> 31) != (insn->disp >> 7));
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| 118 | }
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| 119 | }
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| 120 | }
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| 121 |
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| 122 | static __always_inline
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| 123 | void *text_gen_insn(u8 opcode, const void *addr, const void *dest)
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| 124 | {
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| 125 | static union text_poke_insn insn;
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| 126 | __text_gen_insn(&insn, opcode, addr, dest, text_opcode_size(opcode));
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| 127 | return &insn.text;
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| 128 | }
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| 129 |
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| 130 | extern int after_bootmem;
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| 131 | extern __ro_after_init struct mm_struct *text_poke_mm;
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| 132 | extern __ro_after_init unsigned long text_poke_mm_addr;
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| 133 |
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| 134 | #ifndef CONFIG_UML_X86
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| 135 | static __always_inline
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| 136 | void int3_emulate_jmp(struct pt_regs *regs, unsigned long ip)
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| 137 | {
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| 138 | regs->ip = ip;
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| 139 | }
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| 140 |
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| 141 | static __always_inline
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| 142 | void int3_emulate_push(struct pt_regs *regs, unsigned long val)
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| 143 | {
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| 144 | |
| 145 | * The INT3 handler in entry_64.S adds a gap between the
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| 146 | * stack where the break point happened, and the saving of
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| 147 | * pt_regs. We can extend the original stack because of
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| 148 | * this gap. See the idtentry macro's X86_TRAP_BP logic.
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| 149 | *
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| 150 | * Similarly, entry_32.S will have a gap on the stack for
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| 151 | * (any) hardware exception and pt_regs; see the
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| 152 | * FIXUP_FRAME macro.
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| 153 |
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| 154 | regs->sp -= sizeof(unsigned long);
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| 155 | *(unsigned long *)regs->sp = val;
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| 156 | }
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| 157 |
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| 158 | static __always_inline
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| 159 | unsigned long int3_emulate_pop(struct pt_regs *regs)
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| 160 | {
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| 161 | unsigned long val = *(unsigned long *)regs->sp;
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| 162 | regs->sp += sizeof(unsigned long);
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| 163 | return val;
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| 164 | }
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| 165 |
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| 166 | static __always_inline
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| 167 | void int3_emulate_call(struct pt_regs *regs, unsigned long ip, unsigned long func)
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| 168 | {
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| 169 | int3_emulate_push(regs, ip);
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| 170 | int3_emulate_jmp(regs, func);
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| 171 | }
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| 172 |
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| 173 | static __always_inline
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| 174 | void int3_emulate_ret(struct pt_regs *regs)
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| 175 | {
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| 176 | unsigned long ip = int3_emulate_pop(regs);
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| 177 | int3_emulate_jmp(regs, ip);
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| 178 | }
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| 179 |
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| 180 | static __always_inline
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| 181 | bool __emulate_cc(unsigned long flags, u8 cc)
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| 182 | {
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| 183 | static const unsigned long cc_mask[6] = {
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| 184 | [0] = X86_EFLAGS_OF,
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| 185 | [1] = X86_EFLAGS_CF,
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| 186 | [2] = X86_EFLAGS_ZF,
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| 187 | [3] = X86_EFLAGS_CF | X86_EFLAGS_ZF,
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| 188 | [4] = X86_EFLAGS_SF,
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| 189 | [5] = X86_EFLAGS_PF,
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| 190 | };
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| 191 |
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| 192 | bool invert = cc & 1;
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| 193 | bool match;
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| 194 |
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| 195 | if (cc < 0xc) {
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| 196 | match = flags & cc_mask[cc >> 1];
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| 197 | } else {
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| 198 | match = ((flags & X86_EFLAGS_SF) >> X86_EFLAGS_SF_BIT) ^
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| 199 | ((flags & X86_EFLAGS_OF) >> X86_EFLAGS_OF_BIT);
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| 200 | if (cc >= 0xe)
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| 201 | match = match || (flags & X86_EFLAGS_ZF);
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| 202 | }
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| 203 |
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| 204 | return (match && !invert) || (!match && invert);
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| 205 | }
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| 206 |
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| 207 | static __always_inline
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| 208 | void int3_emulate_jcc(struct pt_regs *regs, u8 cc, unsigned long ip, unsigned long disp)
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| 209 | {
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| 210 | if (__emulate_cc(regs->flags, cc))
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| 211 | ip += disp;
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| 212 |
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| 213 | int3_emulate_jmp(regs, ip);
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| 214 | }
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| 215 |
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| 216 | #endif
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| 217 |
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| 218 | #endif
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