| 1 | |
| 2 | |
| 3 | * Common corrected MCE threshold handler code:
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| 4 |
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| 5 | #include <linux/interrupt.h>
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| 6 | #include <linux/kernel.h>
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| 7 |
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| 8 | #include <asm/irq_vectors.h>
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| 9 | #include <asm/traps.h>
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| 10 | #include <asm/apic.h>
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| 11 | #include <asm/mce.h>
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| 12 | #include <asm/trace/irq_vectors.h>
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| 13 |
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| 14 | #include "internal.h"
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| 15 |
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| 16 | static u32 mce_apei_thr_limit;
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| 17 |
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| 18 | void mce_save_apei_thr_limit(u32 thr_limit)
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| 19 | {
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| 20 | mce_apei_thr_limit = thr_limit;
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| 21 | pr_info("HEST corrected error threshold limit: %u\n", thr_limit);
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| 22 | }
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| 23 |
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| 24 | u32 mce_get_apei_thr_limit(void)
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| 25 | {
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| 26 | return mce_apei_thr_limit;
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| 27 | }
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| 28 |
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| 29 | static void default_threshold_interrupt(void)
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| 30 | {
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| 31 | pr_err("Unexpected threshold interrupt at vector %x\n",
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| 32 | THRESHOLD_APIC_VECTOR);
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| 33 | }
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| 34 |
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| 35 | void (*mce_threshold_vector)(void) = default_threshold_interrupt;
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| 36 |
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| 37 | DEFINE_IDTENTRY_SYSVEC(sysvec_threshold)
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| 38 | {
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| 39 | trace_threshold_apic_entry(THRESHOLD_APIC_VECTOR);
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| 40 | inc_irq_stat(THRESHOLD_APIC);
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| 41 | mce_threshold_vector();
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| 42 | trace_threshold_apic_exit(THRESHOLD_APIC_VECTOR);
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| 43 | apic_eoi();
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| 44 | }
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| 45 |
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| 46 | DEFINE_PER_CPU(struct mca_storm_desc, storm_desc);
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| 47 |
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| 48 | void mce_inherit_storm(unsigned int bank)
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| 49 | {
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| 50 | struct mca_storm_desc *storm = this_cpu_ptr(&storm_desc);
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| 51 |
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| 52 | |
| 53 | * Previous CPU owning this bank had put it into storm mode,
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| 54 | * but the precise history of that storm is unknown. Assume
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| 55 | * the worst (all recent polls of the bank found a valid error
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| 56 | * logged). This will avoid the new owner prematurely declaring
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| 57 | * the storm has ended.
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| 58 |
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| 59 | storm->banks[bank].history = ~0ull;
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| 60 | storm->banks[bank].timestamp = jiffies;
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| 61 | }
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| 62 |
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| 63 | bool mce_get_storm_mode(void)
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| 64 | {
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| 65 | return __this_cpu_read(storm_desc.poll_mode);
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| 66 | }
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| 67 |
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| 68 | void mce_set_storm_mode(bool storm)
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| 69 | {
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| 70 | __this_cpu_write(storm_desc.poll_mode, storm);
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| 71 | }
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| 72 |
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| 73 | static void mce_handle_storm(unsigned int bank, bool on)
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| 74 | {
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| 75 | switch (boot_cpu_data.x86_vendor) {
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| 76 | case X86_VENDOR_INTEL:
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| 77 | mce_intel_handle_storm(bank, on);
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| 78 | break;
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| 79 | case X86_VENDOR_AMD:
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| 80 | mce_amd_handle_storm(bank, on);
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| 81 | break;
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| 82 | }
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| 83 | }
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| 84 |
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| 85 | void cmci_storm_begin(unsigned int bank)
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| 86 | {
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| 87 | struct mca_storm_desc *storm = this_cpu_ptr(&storm_desc);
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| 88 |
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| 89 | __set_bit(bank, this_cpu_ptr(mce_poll_banks));
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| 90 | storm->banks[bank].in_storm_mode = true;
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| 91 |
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| 92 | |
| 93 | * If this is the first bank on this CPU to enter storm mode
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| 94 | * start polling.
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| 95 |
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| 96 | if (++storm->stormy_bank_count == 1)
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| 97 | mce_timer_kick(true);
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| 98 | }
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| 99 |
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| 100 | void cmci_storm_end(unsigned int bank)
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| 101 | {
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| 102 | struct mca_storm_desc *storm = this_cpu_ptr(&storm_desc);
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| 103 |
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| 104 | if (!mce_flags.amd_threshold)
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| 105 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
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| 106 | storm->banks[bank].history = 0;
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| 107 | storm->banks[bank].in_storm_mode = false;
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| 108 |
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| 109 |
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| 110 | if (!--storm->stormy_bank_count)
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| 111 | mce_timer_kick(false);
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| 112 | }
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| 113 |
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| 114 | void mce_track_storm(struct mce *mce)
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| 115 | {
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| 116 | struct mca_storm_desc *storm = this_cpu_ptr(&storm_desc);
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| 117 | unsigned long now = jiffies, delta;
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| 118 | unsigned int shift = 1;
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| 119 | u64 history = 0;
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| 120 |
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| 121 |
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| 122 | if (storm->banks[mce->bank].poll_only)
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| 123 | return;
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| 124 |
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| 125 | |
| 126 | * When a bank is in storm mode it is polled once per second and
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| 127 | * the history mask will record about the last minute of poll results.
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| 128 | * If it is not in storm mode, then the bank is only checked when
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| 129 | * there is a CMCI interrupt. Check how long it has been since
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| 130 | * this bank was last checked, and adjust the amount of "shift"
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| 131 | * to apply to history.
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| 132 |
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| 133 | if (!storm->banks[mce->bank].in_storm_mode) {
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| 134 | delta = now - storm->banks[mce->bank].timestamp;
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| 135 | shift = (delta + HZ) / HZ;
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| 136 | }
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| 137 |
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| 138 |
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| 139 | if (shift < NUM_HISTORY_BITS)
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| 140 | history = storm->banks[mce->bank].history << shift;
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| 141 |
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| 142 | storm->banks[mce->bank].timestamp = now;
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| 143 |
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| 144 |
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| 145 | if ((mce->status & MCI_STATUS_VAL) && mce_is_correctable(mce))
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| 146 | history |= 1;
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| 147 |
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| 148 | storm->banks[mce->bank].history = history;
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| 149 |
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| 150 | if (storm->banks[mce->bank].in_storm_mode) {
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| 151 | if (history & GENMASK_ULL(STORM_END_POLL_THRESHOLD, 0))
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| 152 | return;
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| 153 | printk_deferred(KERN_NOTICE "CPU%d BANK%d CMCI storm subsided\n", smp_processor_id(), mce->bank);
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| 154 | mce_handle_storm(mce->bank, false);
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| 155 | cmci_storm_end(mce->bank);
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| 156 | } else {
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| 157 | if (hweight64(history) < STORM_BEGIN_THRESHOLD)
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| 158 | return;
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| 159 | printk_deferred(KERN_NOTICE "CPU%d BANK%d CMCI storm detected\n", smp_processor_id(), mce->bank);
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| 160 | mce_handle_storm(mce->bank, true);
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| 161 | cmci_storm_begin(mce->bank);
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| 162 | }
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| 163 | }
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