| 1 | |
| 2 | * include/asm-xtensa/cache.h
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| 3 | *
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| 4 | * This file is subject to the terms and conditions of the GNU General Public
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| 5 | * License. See the file "COPYING" in the main directory of this archive
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| 6 | * for more details.
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| 7 | *
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| 8 | * (C) 2001 - 2005 Tensilica Inc.
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| 9 |
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| 10 |
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| 11 | #ifndef _XTENSA_CACHE_H
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| 12 | #define _XTENSA_CACHE_H
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| 13 |
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| 14 | #include <asm/core.h>
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| 15 |
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| 16 | #define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
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| 17 | #define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE
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| 18 | #define SMP_CACHE_BYTES L1_CACHE_BYTES
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| 19 |
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| 20 | #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
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| 21 | #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
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| 22 | #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
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| 23 | #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
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| 24 |
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| 25 |
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| 26 | #if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
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| 27 | # define CACHE_WAY_SIZE DCACHE_WAY_SIZE
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| 28 | #else
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| 29 | # define CACHE_WAY_SIZE ICACHE_WAY_SIZE
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| 30 | #endif
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| 31 |
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| 32 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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| 33 |
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| 34 | |
| 35 | * R/O after init is actually writable, it cannot go to .rodata
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| 36 | * according to vmlinux linker script.
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| 37 |
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| 38 | #define __ro_after_init __read_mostly
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| 39 |
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| 40 | #endif
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