| 1 | |
| 2 | * include/asm-xtensa/cacheasm.h
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| 3 | *
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| 4 | * This file is subject to the terms and conditions of the GNU General Public
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| 5 | * License. See the file "COPYING" in the main directory of this archive
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| 6 | * for more details.
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| 7 | *
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| 8 | * Copyright (C) 2006 Tensilica Inc.
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| 9 |
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| 10 |
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| 11 | #include <asm/cache.h>
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| 12 | #include <asm/asmmacro.h>
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| 13 | #include <linux/stringify.h>
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| 14 |
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| 15 | |
| 16 | * Define cache functions as macros here so that they can be used
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| 17 | * by the kernel and boot loader. We should consider moving them to a
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| 18 | * library that can be linked by both.
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| 19 | *
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| 20 | * Locking
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| 21 | *
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| 22 | * ___unlock_dcache_all
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| 23 | * ___unlock_icache_all
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| 24 | *
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| 25 | * Flush and invaldating
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| 26 | *
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| 27 | * ___flush_invalidate_dcache_{all|range|page}
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| 28 | * ___flush_dcache_{all|range|page}
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| 29 | * ___invalidate_dcache_{all|range|page}
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| 30 | * ___invalidate_icache_{all|range|page}
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| 31 | *
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| 32 |
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| 33 |
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| 34 |
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| 35 | .macro __loop_cache_unroll ar at insn size line_width max_immed
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| 36 |
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| 37 | .if (1 << (\line_width)) > (\max_immed)
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| 38 | .set _reps, 1
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| 39 | .elseif (2 << (\line_width)) > (\max_immed)
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| 40 | .set _reps, 2
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| 41 | .else
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| 42 | .set _reps, 4
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| 43 | .endif
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| 44 |
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| 45 | __loopi \ar, \at, \size, (_reps << (\line_width))
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| 46 | .set _index, 0
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| 47 | .rep _reps
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| 48 | \insn \ar, _index << (\line_width)
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| 49 | .set _index, _index + 1
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| 50 | .endr
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| 51 | __endla \ar, \at, _reps << (\line_width)
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| 52 |
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| 53 | .endm
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| 54 |
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| 55 |
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| 56 | .macro __loop_cache_all ar at insn size line_width max_immed
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| 57 |
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| 58 | movi \ar, 0
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| 59 | __loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed
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| 60 |
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| 61 | .endm
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| 62 |
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| 63 |
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| 64 | .macro __loop_cache_range ar as at insn line_width
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| 65 |
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| 66 | extui \at, \ar, 0, \line_width
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| 67 | add \as, \as, \at
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| 68 |
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| 69 | __loops \ar, \as, \at, \line_width
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| 70 | \insn \ar, 0
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| 71 | __endla \ar, \at, (1 << (\line_width))
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| 72 |
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| 73 | .endm
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| 74 |
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| 75 |
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| 76 | .macro __loop_cache_page ar at insn line_width max_immed
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| 77 |
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| 78 | __loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed
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| 79 |
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| 80 | .endm
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| 81 |
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| 82 |
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| 83 | .macro ___unlock_dcache_all ar at
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| 84 |
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| 85 | #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
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| 86 | __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
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| 87 | XCHAL_DCACHE_LINEWIDTH 240
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| 88 | #endif
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| 89 |
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| 90 | .endm
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| 91 |
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| 92 |
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| 93 | .macro ___unlock_icache_all ar at
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| 94 |
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| 95 | #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
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| 96 | __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
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| 97 | XCHAL_ICACHE_LINEWIDTH 240
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| 98 | #endif
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| 99 |
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| 100 | .endm
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| 101 |
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| 102 |
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| 103 | .macro ___flush_invalidate_dcache_all ar at
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| 104 |
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| 105 | #if XCHAL_DCACHE_SIZE
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| 106 | __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
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| 107 | XCHAL_DCACHE_LINEWIDTH 240
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| 108 | #endif
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| 109 |
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| 110 | .endm
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| 111 |
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| 112 |
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| 113 | .macro ___flush_dcache_all ar at
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| 114 |
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| 115 | #if XCHAL_DCACHE_SIZE
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| 116 | __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
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| 117 | XCHAL_DCACHE_LINEWIDTH 240
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| 118 | #endif
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| 119 |
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| 120 | .endm
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| 121 |
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| 122 |
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| 123 | .macro ___invalidate_dcache_all ar at
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| 124 |
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| 125 | #if XCHAL_DCACHE_SIZE
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| 126 | __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
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| 127 | XCHAL_DCACHE_LINEWIDTH 1020
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| 128 | #endif
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| 129 |
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| 130 | .endm
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| 131 |
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| 132 |
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| 133 | .macro ___invalidate_icache_all ar at
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| 134 |
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| 135 | #if XCHAL_ICACHE_SIZE
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| 136 | __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
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| 137 | XCHAL_ICACHE_LINEWIDTH 1020
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| 138 | #endif
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| 139 |
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| 140 | .endm
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| 141 |
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| 142 |
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| 143 |
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| 144 | .macro ___flush_invalidate_dcache_range ar as at
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| 145 |
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| 146 | #if XCHAL_DCACHE_SIZE
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| 147 | __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
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| 148 | #endif
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| 149 |
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| 150 | .endm
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| 151 |
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| 152 |
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| 153 | .macro ___flush_dcache_range ar as at
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| 154 |
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| 155 | #if XCHAL_DCACHE_SIZE
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| 156 | __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
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| 157 | #endif
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| 158 |
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| 159 | .endm
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| 160 |
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| 161 |
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| 162 | .macro ___invalidate_dcache_range ar as at
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| 163 |
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| 164 | #if XCHAL_DCACHE_SIZE
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| 165 | __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
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| 166 | #endif
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| 167 |
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| 168 | .endm
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| 169 |
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| 170 |
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| 171 | .macro ___invalidate_icache_range ar as at
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| 172 |
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| 173 | #if XCHAL_ICACHE_SIZE
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| 174 | __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
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| 175 | #endif
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| 176 |
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| 177 | .endm
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| 178 |
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| 179 |
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| 180 |
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| 181 | .macro ___flush_invalidate_dcache_page ar as
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| 182 |
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| 183 | #if XCHAL_DCACHE_SIZE
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| 184 | __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
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| 185 | #endif
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| 186 |
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| 187 | .endm
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| 188 |
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| 189 |
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| 190 | .macro ___flush_dcache_page ar as
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| 191 |
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| 192 | #if XCHAL_DCACHE_SIZE
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| 193 | __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
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| 194 | #endif
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| 195 |
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| 196 | .endm
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| 197 |
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| 198 |
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| 199 | .macro ___invalidate_dcache_page ar as
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| 200 |
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| 201 | #if XCHAL_DCACHE_SIZE
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| 202 | __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020
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| 203 | #endif
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| 204 |
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| 205 | .endm
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| 206 |
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| 207 |
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| 208 | .macro ___invalidate_icache_page ar as
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| 209 |
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| 210 | #if XCHAL_ICACHE_SIZE
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| 211 | __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
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| 212 | #endif
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| 213 |
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| 214 | .endm
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