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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * include/asm-xtensa/pgtable.h
4 *
5 * Copyright (C) 2001 - 2013 Tensilica Inc.
6 */
7
8#ifndef _XTENSA_PGTABLE_H
9#define _XTENSA_PGTABLE_H
10
11#include <asm/page.h>
12#include <asm/kmem_layout.h>
13#include <asm-generic/pgtable-nopmd.h>
14
15/*
16 * We only use two ring levels, user and kernel space.
17 */
18
19#ifdef CONFIG_MMU
20#define USER_RING 1 /* user ring level */
21#else
22#define USER_RING 0
23#endif
24#define KERNEL_RING 0 /* kernel ring level */
25
26/*
27 * The Xtensa architecture port of Linux has a two-level page table system,
28 * i.e. the logical three-level Linux page table layout is folded.
29 * Each task has the following memory page tables:
30 *
31 * PGD table (page directory), ie. 3rd-level page table:
32 * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
33 * (Architectures that don't have the PMD folded point to the PMD tables)
34 *
35 * The pointer to the PGD table for a given task can be retrieved from
36 * the task structure (struct task_struct*) t, e.g. current():
37 * (t->mm ? t->mm : t->active_mm)->pgd
38 *
39 * PMD tables (page middle-directory), ie. 2nd-level page tables:
40 * Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
41 *
42 * PTE tables (page table entry), ie. 1st-level page tables:
43 * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
44 * invalid_pte_table for absent mappings.
45 *
46 * The individual pages are 4 kB big with special pages for the empty_zero_page.
47 */
48
49#define PGDIR_SHIFT 22
50#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
51#define PGDIR_MASK (~(PGDIR_SIZE-1))
52
53/*
54 * Entries per page directory level: we use two-level, so
55 * we don't really have any PMD directory physically.
56 */
57#define PTRS_PER_PTE 1024
58#define PTRS_PER_PTE_SHIFT 10
59#define PTRS_PER_PGD 1024
60#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
61
62#ifdef CONFIG_MMU
63/*
64 * Virtual memory area. We keep a distance to other memory regions to be
65 * on the safe side. We also use this area for cache aliasing.
66 */
67#define VMALLOC_START (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
68#define VMALLOC_END (VMALLOC_START + 0x07FEFFFF)
69#define TLBTEMP_BASE_1 (VMALLOC_START + 0x08000000)
70#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
71#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
72#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
73#else
74#define TLBTEMP_SIZE ICACHE_WAY_SIZE
75#endif
76
77#else
78
79#define VMALLOC_START __XTENSA_UL_CONST(0)
80#define VMALLOC_END __XTENSA_UL_CONST(0xffffffff)
81
82#endif
83
84/*
85 * For the Xtensa architecture, the PTE layout is as follows:
86 *
87 * 31------12 11 10-9 8-6 5-4 3-2 1-0
88 * +-----------------------------------------+
89 * | | Software | HARDWARE |
90 * | PPN | ADW | RI |Attribute|
91 * +-----------------------------------------+
92 * pte_none | MBZ | 01 | 11 | 00 |
93 * +-----------------------------------------+
94 * present | PPN | 0 | 00 | ADW | RI | CA | wx |
95 * +- - - - - - - - - - - - - - - - - - - - -+
96 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 11 | 11 |
97 * +-----------------------------------------+
98 * swap | index | type | 01 | 11 | e0 |
99 * +-----------------------------------------+
100 *
101 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
102 * +-----------------------------------------+
103 * present | PPN | 0 | 00 | ADW | RI | CA | w1 |
104 * +-----------------------------------------+
105 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 01 | 00 |
106 * +-----------------------------------------+
107 *
108 * Legend:
109 * PPN Physical Page Number
110 * ADW software: accessed (young) / dirty / writable
111 * RI ring (0=privileged, 1=user, 2 and 3 are unused)
112 * CA cache attribute: 00 bypass, 01 writeback, 10 writethrough
113 * (11 is invalid and used to mark pages that are not present)
114 * e exclusive marker in swap PTEs
115 * w page is writable (hw)
116 * x page is executable (hw)
117 * index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
118 * (note that the index is always non-zero)
119 * type swap type (5 bits -> 32 types)
120 *
121 * Notes:
122 * - (PROT_NONE) is a special case of 'present' but causes an exception for
123 * any access (read, write, and execute).
124 * - 'multihit-exception' has the highest priority of all MMU exceptions,
125 * so the ring must be set to 'RING_USER' even for 'non-present' pages.
126 * - on older hardware, the exectuable flag was not supported and
127 * used as a 'valid' flag, so it needs to be always set.
128 * - we need to keep track of certain flags in software (dirty and young)
129 * to do this, we use write exceptions and have a separate software w-flag.
130 * - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
131 */
132
133#define _PAGE_ATTRIB_MASK 0xf
134
135#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
136#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
137
138#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
139#define _PAGE_CA_WB (1<<2) /* write-back */
140#define _PAGE_CA_WT (2<<2) /* write-through */
141#define _PAGE_CA_MASK (3<<2)
142#define _PAGE_CA_INVALID (3<<2)
143
144/* We use invalid attribute values to distinguish special pte entries */
145#if XCHAL_HW_VERSION_MAJOR < 2000
146#define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */
147#define _PAGE_NONE 0x04
148#else
149#define _PAGE_HW_VALID 0x00
150#define _PAGE_NONE 0x0f
151#endif
152
153#define _PAGE_USER (1<<4) /* user access (ring=1) */
154
155/* Software */
156#define _PAGE_WRITABLE_BIT 6
157#define _PAGE_WRITABLE (1<<6) /* software: page writable */
158#define _PAGE_DIRTY (1<<7) /* software: page dirty */
159#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
160
161/* We borrow bit 1 to store the exclusive marker in swap PTEs. */
162#define _PAGE_SWP_EXCLUSIVE (1<<1)
163
164#ifdef CONFIG_MMU
165
166#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
167#define _PAGE_PRESENT (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
168
169#define PAGE_NONE __pgprot(_PAGE_NONE | _PAGE_USER)
170#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER)
171#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
172#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER)
173#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
174#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
175#define PAGE_SHARED_EXEC \
176 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
177#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
178#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT)
179#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
180
181#if (DCACHE_WAY_SIZE > PAGE_SIZE)
182# define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
183#else
184# define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
185#endif
186
187#else /* no mmu */
188
189# define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
190# define PAGE_NONE __pgprot(0)
191# define PAGE_SHARED __pgprot(0)
192# define PAGE_COPY __pgprot(0)
193# define PAGE_READONLY __pgprot(0)
194# define PAGE_KERNEL __pgprot(0)
195
196#endif
197
198/*
199 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
200 * the MMU can't do page protection for execute, and considers that the same as
201 * read. Also, write permissions may imply read permissions.
202 * What follows is the closest we can get by reasonable means..
203 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
204 */
205#ifndef __ASSEMBLER__
206
207#define pte_ERROR(e) \
208 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
209#define pgd_ERROR(e) \
210 printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
211
212#ifdef CONFIG_MMU
213extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
214extern void paging_init(void);
215#else
216# define swapper_pg_dir NULL
217static inline void paging_init(void) { }
218#endif
219
220/*
221 * The pmd contains the kernel virtual address of the pte page.
222 */
223#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
224#define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
225#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
226
227/*
228 * pte status.
229 */
230# define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
231#if XCHAL_HW_VERSION_MAJOR < 2000
232# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
233#else
234# define pte_present(pte) \
235 (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \
236 || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
237#endif
238#define pte_clear(mm,addr,ptep) \
239 do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
240
241#define pmd_none(pmd) (!pmd_val(pmd))
242#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
243#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
244#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
245
246static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
247static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
248static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
249
250static inline pte_t pte_wrprotect(pte_t pte)
251 { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
252static inline pte_t pte_mkclean(pte_t pte)
253 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
254static inline pte_t pte_mkold(pte_t pte)
255 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
256static inline pte_t pte_mkdirty(pte_t pte)
257 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
258static inline pte_t pte_mkyoung(pte_t pte)
259 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
260static inline pte_t pte_mkwrite_novma(pte_t pte)
261 { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
262
263#define pgprot_noncached(prot) \
264 ((__pgprot((pgprot_val(prot) & ~_PAGE_CA_MASK) | \
265 _PAGE_CA_BYPASS)))
266
267#define PFN_PTE_SHIFT PAGE_SHIFT
268#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
269#define pte_same(a,b) (pte_val(a) == pte_val(b))
270#define pte_page(x) pfn_to_page(pte_pfn(x))
271#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
272
273static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
274{
275 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
276}
277
278/*
279 * Certain architectures need to do special things when pte's
280 * within a page table are directly modified. Thus, the following
281 * hook is made available.
282 */
283static inline void update_pte(pte_t *ptep, pte_t pteval)
284{
285 *ptep = pteval;
286#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
287 __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
288#endif
289
290}
291
292struct mm_struct;
293
294static inline void set_pte(pte_t *ptep, pte_t pte)
295{
296 update_pte(ptep, pte);
297}
298
299static inline void
300set_pmd(pmd_t *pmdp, pmd_t pmdval)
301{
302 *pmdp = pmdval;
303}
304
305struct vm_area_struct;
306
307static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma,
308 unsigned long addr, pte_t *ptep)
309{
310 pte_t pte = *ptep;
311 if (!pte_young(pte))
312 return false;
313 update_pte(ptep, pte_mkold(pte));
314 return true;
315}
316
317static inline pte_t
318ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
319{
320 pte_t pte = *ptep;
321 pte_clear(mm, addr, ptep);
322 return pte;
323}
324
325static inline void
326ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
327{
328 pte_t pte = *ptep;
329 update_pte(ptep, pte_wrprotect(pte));
330}
331
332/*
333 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
334 * are !pte_none() && !pte_present().
335 */
336#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
337
338#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
339#define __swp_offset(entry) ((entry).val >> 11)
340#define __swp_entry(type,offs) \
341 ((swp_entry_t){(((type) & 0x1f) << 6) | ((offs) << 11) | \
342 _PAGE_CA_INVALID | _PAGE_USER})
343#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
344#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
345
346static inline bool pte_swp_exclusive(pte_t pte)
347{
348 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
349}
350
351static inline pte_t pte_swp_mkexclusive(pte_t pte)
352{
353 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
354 return pte;
355}
356
357static inline pte_t pte_swp_clear_exclusive(pte_t pte)
358{
359 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
360 return pte;
361}
362
363#endif /* !defined (__ASSEMBLER__) */
364
365
366#ifdef __ASSEMBLER__
367
368/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
369 * _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
370 * _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
371 * _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
372 *
373 * Note: We require an additional temporary register which can be the same as
374 * the register that holds the address.
375 *
376 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
377 *
378 */
379#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
380#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
381
382#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
383 _PGD_INDEX(tmp, adr); \
384 addx4 mm, tmp, mm
385
386#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
387 srli pmd, pmd, PAGE_SHIFT; \
388 slli pmd, pmd, PAGE_SHIFT; \
389 addx4 pmd, tmp, pmd
390
391#else
392
393struct vm_fault;
394void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
395 unsigned long address, pte_t *ptep, unsigned int nr);
396#define update_mmu_cache(vma, address, ptep) \
397 update_mmu_cache_range(NULL, vma, address, ptep, 1)
398
399typedef pte_t *pte_addr_t;
400
401void update_mmu_tlb_range(struct vm_area_struct *vma,
402 unsigned long address, pte_t *ptep, unsigned int nr);
403#define update_mmu_tlb_range update_mmu_tlb_range
404
405#endif /* !defined (__ASSEMBLER__) */
406
407#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
408#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
409#define __HAVE_ARCH_PTEP_SET_WRPROTECT
410#define __HAVE_ARCH_PTEP_MKDIRTY
411#define __HAVE_ARCH_PTE_SAME
412/* We provide our own get_unmapped_area to cope with
413 * SHM area cache aliasing for userland.
414 */
415#define HAVE_ARCH_UNMAPPED_AREA
416
417#endif /* _XTENSA_PGTABLE_H */