| 1 | |
| 2 |
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| 3 |
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| 4 | #include <linux/clk.h>
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| 5 | #include <linux/delay.h>
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| 6 | #include <linux/dev_printk.h>
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| 7 | #include <linux/dma-mapping.h>
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| 8 | #include <linux/err.h>
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| 9 | #include <linux/iommu.h>
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| 10 | #include <linux/platform_device.h>
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| 11 | #include <linux/pm_runtime.h>
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| 12 | #include <linux/reset.h>
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| 13 |
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| 14 | #include "rocket_core.h"
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| 15 | #include "rocket_job.h"
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| 16 |
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| 17 | int rocket_core_init(struct rocket_core *core)
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| 18 | {
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| 19 | struct device *dev = core->dev;
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| 20 | struct platform_device *pdev = to_platform_device(dev);
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| 21 | u32 version;
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| 22 | int err = 0;
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| 23 |
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| 24 | core->resets[0].id = "srst_a";
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| 25 | core->resets[1].id = "srst_h";
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| 26 | err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets),
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| 27 | core->resets);
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| 28 | if (err)
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| 29 | return dev_err_probe(dev, err, "failed to get resets for core %d\n", core->index);
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| 30 |
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| 31 | err = devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks);
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| 32 | if (err)
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| 33 | return dev_err_probe(dev, err, "failed to get clocks for core %d\n", core->index);
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| 34 |
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| 35 | core->pc_iomem = devm_platform_ioremap_resource_byname(pdev, "pc");
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| 36 | if (IS_ERR(core->pc_iomem)) {
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| 37 | dev_err(dev, "couldn't find PC registers %ld\n", PTR_ERR(core->pc_iomem));
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| 38 | return PTR_ERR(core->pc_iomem);
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| 39 | }
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| 40 |
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| 41 | core->cna_iomem = devm_platform_ioremap_resource_byname(pdev, "cna");
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| 42 | if (IS_ERR(core->cna_iomem)) {
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| 43 | dev_err(dev, "couldn't find CNA registers %ld\n", PTR_ERR(core->cna_iomem));
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| 44 | return PTR_ERR(core->cna_iomem);
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| 45 | }
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| 46 |
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| 47 | core->core_iomem = devm_platform_ioremap_resource_byname(pdev, "core");
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| 48 | if (IS_ERR(core->core_iomem)) {
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| 49 | dev_err(dev, "couldn't find CORE registers %ld\n", PTR_ERR(core->core_iomem));
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| 50 | return PTR_ERR(core->core_iomem);
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| 51 | }
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| 52 |
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| 53 | dma_set_max_seg_size(dev, UINT_MAX);
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| 54 |
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| 55 | err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
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| 56 | if (err)
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| 57 | return err;
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| 58 |
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| 59 | core->iommu_group = iommu_group_get(dev);
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| 60 |
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| 61 | err = rocket_job_init(core);
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| 62 | if (err) {
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| 63 | iommu_group_put(core->iommu_group);
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| 64 | core->iommu_group = NULL;
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| 65 | return err;
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| 66 | }
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| 67 |
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| 68 | pm_runtime_use_autosuspend(dev);
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| 69 |
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| 70 | |
| 71 | * As this NPU will be most often used as part of a media pipeline that
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| 72 | * ends presenting in a display, choose 50 ms (~3 frames at 60Hz) as an
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| 73 | * autosuspend delay as that will keep the device powered up while the
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| 74 | * pipeline is running.
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| 75 |
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| 76 | pm_runtime_set_autosuspend_delay(dev, 50);
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| 77 |
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| 78 | pm_runtime_enable(dev);
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| 79 |
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| 80 | err = pm_runtime_resume_and_get(dev);
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| 81 | if (err) {
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| 82 | rocket_core_fini(core);
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| 83 | return err;
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| 84 | }
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| 85 |
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| 86 | version = rocket_pc_readl(core, VERSION);
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| 87 | version += rocket_pc_readl(core, VERSION_NUM) & 0xffff;
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| 88 |
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| 89 | pm_runtime_mark_last_busy(dev);
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| 90 | pm_runtime_put_autosuspend(dev);
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| 91 |
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| 92 | dev_info(dev, "Rockchip NPU core %d version: %d\n", core->index, version);
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| 93 |
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| 94 | return 0;
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| 95 | }
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| 96 |
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| 97 | void rocket_core_fini(struct rocket_core *core)
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| 98 | {
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| 99 | pm_runtime_dont_use_autosuspend(core->dev);
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| 100 | pm_runtime_disable(core->dev);
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| 101 | iommu_group_put(core->iommu_group);
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| 102 | core->iommu_group = NULL;
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| 103 | rocket_job_fini(core);
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| 104 | }
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| 105 |
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| 106 | void rocket_core_reset(struct rocket_core *core)
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| 107 | {
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| 108 | reset_control_bulk_assert(ARRAY_SIZE(core->resets), core->resets);
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| 109 |
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| 110 | udelay(10);
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| 111 |
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| 112 | reset_control_bulk_deassert(ARRAY_SIZE(core->resets), core->resets);
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| 113 | }
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