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1// SPDX-License-Identifier: GPL-2.0
2//
3// Register cache access API
4//
5// Copyright 2011 Wolfson Microelectronics plc
6//
7// Author: Dimitris Papastamos <[email protected]>
8
9#include <linux/bsearch.h>
10#include <linux/device.h>
11#include <linux/export.h>
12#include <linux/slab.h>
13#include <linux/sort.h>
14
15#include "trace.h"
16#include "internal.h"
17
18static const struct regcache_ops *cache_types[] = {
19 &regcache_flat_sparse_ops,
20 &regcache_rbtree_ops,
21 &regcache_maple_ops,
22 &regcache_flat_ops,
23};
24
25static int regcache_defaults_cmp(const void *a, const void *b)
26{
27 const struct reg_default *x = a;
28 const struct reg_default *y = b;
29
30 if (x->reg > y->reg)
31 return 1;
32 else if (x->reg < y->reg)
33 return -1;
34 else
35 return 0;
36}
37
38void regcache_sort_defaults(struct reg_default *defaults, unsigned int ndefaults)
39{
40 sort(defaults, ndefaults, sizeof(*defaults),
41 regcache_defaults_cmp, NULL);
42}
43EXPORT_SYMBOL_GPL(regcache_sort_defaults);
44
45static int regcache_count_cacheable_registers(struct regmap *map)
46{
47 unsigned int count;
48
49 /* calculate the size of reg_defaults */
50 count = 0;
51 for (unsigned int i = 0; i < map->num_reg_defaults_raw; i++)
52 if (regmap_readable(map, i * map->reg_stride) &&
53 !regmap_volatile(map, i * map->reg_stride))
54 count++;
55
56 return count;
57}
58
59static int regcache_hw_init(struct regmap *map)
60{
61 int ret;
62 unsigned int reg, val;
63 void *tmp_buf;
64
65 if (!map->reg_defaults_raw) {
66 bool cache_bypass = map->cache_bypass;
67 dev_dbg(map->dev, "No cache defaults, reading back from HW\n");
68
69 /* Bypass the cache access till data read from HW */
70 map->cache_bypass = true;
71 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
72 if (!tmp_buf)
73 return -ENOMEM;
74 ret = regmap_raw_read(map, 0, tmp_buf,
75 map->cache_size_raw);
76 map->cache_bypass = cache_bypass;
77 if (ret == 0) {
78 map->reg_defaults_raw = tmp_buf;
79 map->cache_free = true;
80 } else {
81 kfree(tmp_buf);
82 }
83 }
84
85 /* fill the reg_defaults */
86 for (unsigned int i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
87 reg = i * map->reg_stride;
88
89 if (!regmap_readable(map, reg))
90 continue;
91
92 if (regmap_volatile(map, reg))
93 continue;
94
95 if (map->reg_defaults_raw) {
96 val = regcache_get_val(map, map->reg_defaults_raw, i);
97 } else {
98 bool cache_bypass = map->cache_bypass;
99
100 map->cache_bypass = true;
101 ret = regmap_read(map, reg, &val);
102 map->cache_bypass = cache_bypass;
103 if (ret != 0) {
104 dev_err(map->dev, "Failed to read %x: %d\n",
105 reg, ret);
106 return ret;
107 }
108 }
109
110 map->reg_defaults[j].reg = reg;
111 map->reg_defaults[j].def = val;
112 j++;
113 }
114
115 return 0;
116}
117
118static void regcache_hw_exit(struct regmap *map)
119{
120 if (map->cache_free)
121 kfree(map->reg_defaults_raw);
122}
123
124int regcache_init(struct regmap *map, const struct regmap_config *config)
125{
126 bool sort_defaults = false;
127 unsigned int reg_prev = 0;
128 int count = 0;
129 int ret;
130 int i;
131 void *tmp_buf;
132
133 if (map->cache_type == REGCACHE_NONE) {
134 if (config->reg_defaults || config->num_reg_defaults_raw)
135 dev_warn(map->dev,
136 "No cache used with register defaults set!\n");
137
138 map->cache_bypass = true;
139 return 0;
140 }
141
142 if (config->reg_defaults && !config->num_reg_defaults) {
143 dev_err(map->dev,
144 "Register defaults are set without the number!\n");
145 return -EINVAL;
146 }
147
148 if (config->num_reg_defaults && !config->reg_defaults) {
149 dev_err(map->dev,
150 "Register defaults number are set without the reg!\n");
151 return -EINVAL;
152 }
153
154 for (i = 0; i < config->num_reg_defaults; i++) {
155 if (config->reg_defaults[i].reg % map->reg_stride)
156 return -EINVAL;
157
158 if (reg_prev > config->reg_defaults[i].reg)
159 sort_defaults = true;
160
161 reg_prev = config->reg_defaults[i].reg;
162 }
163
164 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
165 if (cache_types[i]->type == map->cache_type)
166 break;
167
168 if (i == ARRAY_SIZE(cache_types)) {
169 dev_err(map->dev, "Could not match cache type: %d\n",
170 map->cache_type);
171 return -EINVAL;
172 }
173
174 map->num_reg_defaults = config->num_reg_defaults;
175 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
176 map->reg_defaults_raw = config->reg_defaults_raw;
177 map->cache_word_size = BITS_TO_BYTES(config->val_bits);
178 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
179
180 map->cache = NULL;
181 map->cache_ops = cache_types[i];
182
183 if (!map->cache_ops->read ||
184 !map->cache_ops->write ||
185 !map->cache_ops->name)
186 return -EINVAL;
187
188 /* We still need to ensure that the reg_defaults
189 * won't vanish from under us. We'll need to make
190 * a copy of it.
191 */
192 if (config->reg_defaults) {
193 tmp_buf = kmemdup_array(config->reg_defaults, map->num_reg_defaults,
194 sizeof(*map->reg_defaults), GFP_KERNEL);
195 if (!tmp_buf)
196 return -ENOMEM;
197
198 /* regcache_lookup_reg() bsearch()es this array */
199 if (sort_defaults) {
200 dev_warn(map->dev,
201 "Driver needs fixing: Unsorted reg_defaults, sorting the copy\n");
202 regcache_sort_defaults(tmp_buf, map->num_reg_defaults);
203 }
204 map->reg_defaults = tmp_buf;
205 } else if (map->num_reg_defaults_raw) {
206 count = regcache_count_cacheable_registers(map);
207 if (!count)
208 map->cache_bypass = true;
209
210 /* All registers are unreadable or volatile, so just bypass */
211 if (map->cache_bypass)
212 return 0;
213
214 map->num_reg_defaults = count;
215 map->reg_defaults = kmalloc_objs(struct reg_default, count);
216 if (!map->reg_defaults)
217 return -ENOMEM;
218 }
219
220 if (!map->max_register_is_set && map->num_reg_defaults_raw) {
221 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
222 map->max_register_is_set = true;
223 }
224
225 if (map->cache_ops->init) {
226 dev_dbg(map->dev, "Initializing %s cache\n",
227 map->cache_ops->name);
228 ret = map->cache_ops->init(map);
229 if (ret)
230 goto err_free_reg_defaults;
231 }
232
233 /*
234 * Some devices such as PMICs don't have cache defaults,
235 * we cope with this by reading back the HW registers and
236 * crafting the cache defaults by hand.
237 */
238 if (count) {
239 ret = regcache_hw_init(map);
240 if (ret)
241 goto err_exit;
242 }
243
244 if (map->cache_ops->populate &&
245 (map->num_reg_defaults || map->reg_default_cb)) {
246 dev_dbg(map->dev, "Populating %s cache\n", map->cache_ops->name);
247 map->lock(map->lock_arg);
248 ret = map->cache_ops->populate(map);
249 map->unlock(map->lock_arg);
250 if (ret)
251 goto err_free;
252 }
253 return 0;
254
255err_free:
256 regcache_hw_exit(map);
257err_exit:
258 if (map->cache_ops->exit) {
259 dev_dbg(map->dev, "Destroying %s cache\n", map->cache_ops->name);
260 map->cache_ops->exit(map);
261 }
262err_free_reg_defaults:
263 kfree(map->reg_defaults);
264
265 return ret;
266}
267
268void regcache_exit(struct regmap *map)
269{
270 if (map->cache_type == REGCACHE_NONE)
271 return;
272
273 BUG_ON(!map->cache_ops);
274
275 regcache_hw_exit(map);
276
277 if (map->cache_ops->exit) {
278 dev_dbg(map->dev, "Destroying %s cache\n",
279 map->cache_ops->name);
280 map->cache_ops->exit(map);
281 }
282
283 kfree(map->reg_defaults);
284}
285
286/**
287 * regcache_read - Fetch the value of a given register from the cache.
288 *
289 * @map: map to configure.
290 * @reg: The register index.
291 * @value: The value to be returned.
292 *
293 * Return a negative value on failure, 0 on success.
294 */
295int regcache_read(struct regmap *map,
296 unsigned int reg, unsigned int *value)
297{
298 int ret;
299
300 if (map->cache_type == REGCACHE_NONE)
301 return -EINVAL;
302
303 BUG_ON(!map->cache_ops);
304
305 if (!regmap_volatile(map, reg)) {
306 ret = map->cache_ops->read(map, reg, value);
307
308 if (ret == 0)
309 trace_regmap_reg_read_cache(map, reg, *value);
310
311 return ret;
312 }
313
314 return -EINVAL;
315}
316
317/**
318 * regcache_write - Set the value of a given register in the cache.
319 *
320 * @map: map to configure.
321 * @reg: The register index.
322 * @value: The new register value.
323 *
324 * Return a negative value on failure, 0 on success.
325 */
326int regcache_write(struct regmap *map,
327 unsigned int reg, unsigned int value)
328{
329 if (map->cache_type == REGCACHE_NONE)
330 return 0;
331
332 BUG_ON(!map->cache_ops);
333
334 if (!regmap_volatile(map, reg))
335 return map->cache_ops->write(map, reg, value);
336
337 return 0;
338}
339
340bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
341 unsigned int val)
342{
343 int ret;
344
345 if (!regmap_writeable(map, reg))
346 return false;
347
348 /* If we don't know the chip just got reset, then sync everything. */
349 if (!map->no_sync_defaults)
350 return true;
351
352 /* Is this the hardware default? If so skip. */
353 ret = regcache_lookup_reg(map, reg);
354 if (ret >= 0 && val == map->reg_defaults[ret].def)
355 return false;
356 return true;
357}
358
359static int regcache_default_sync(struct regmap *map, unsigned int min,
360 unsigned int max)
361{
362 unsigned int reg;
363
364 for (reg = min; reg <= max; reg += map->reg_stride) {
365 unsigned int val;
366 int ret;
367
368 if (regmap_volatile(map, reg) ||
369 !regmap_writeable(map, reg))
370 continue;
371
372 ret = regcache_read(map, reg, &val);
373 if (ret == -ENOENT)
374 continue;
375 if (ret)
376 return ret;
377
378 if (!regcache_reg_needs_sync(map, reg, val))
379 continue;
380
381 map->cache_bypass = true;
382 ret = _regmap_write(map, reg, val);
383 map->cache_bypass = false;
384 if (ret) {
385 dev_err(map->dev, "Unable to sync register %#x. %d\n",
386 reg, ret);
387 return ret;
388 }
389 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
390 }
391
392 return 0;
393}
394
395static int rbtree_all(const void *key, const struct rb_node *node)
396{
397 return 0;
398}
399
400/**
401 * regcache_sync - Sync the register cache with the hardware.
402 *
403 * @map: map to configure.
404 *
405 * Any registers that should not be synced should be marked as
406 * volatile. In general drivers can choose not to use the provided
407 * syncing functionality if they so require.
408 *
409 * This pushes cached changes made while cache_only (e.g. suspend) down
410 * to hardware. The caller must disable cache_only before calling this
411 * function.
412 *
413 * Return a negative value on failure, 0 on success.
414 */
415int regcache_sync(struct regmap *map)
416{
417 int sync_ret = 0;
418 int selector_ret = 0;
419 unsigned int i;
420 const char *name;
421 bool bypass;
422 struct rb_node *node;
423
424 if (WARN_ON(map->cache_type == REGCACHE_NONE))
425 return -EINVAL;
426
427 BUG_ON(!map->cache_ops);
428
429 map->lock(map->lock_arg);
430
431 if (WARN_ON(map->cache_only)) {
432 map->unlock(map->lock_arg);
433 return -EINVAL;
434 }
435
436 /* Remember the initial bypass state */
437 bypass = map->cache_bypass;
438 dev_dbg(map->dev, "Syncing %s cache\n",
439 map->cache_ops->name);
440 name = map->cache_ops->name;
441 trace_regcache_sync(map, name, "start");
442
443 if (!map->cache_dirty)
444 goto out;
445
446 /* Apply any patch first */
447 map->cache_bypass = true;
448 for (i = 0; i < map->patch_regs; i++) {
449 sync_ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
450 if (sync_ret != 0) {
451 dev_err(map->dev, "Failed to write %x = %x: %d\n",
452 map->patch[i].reg, map->patch[i].def, sync_ret);
453 goto out;
454 }
455 }
456 map->cache_bypass = false;
457
458 if (map->cache_ops->sync)
459 sync_ret = map->cache_ops->sync(map, 0, map->max_register);
460 else
461 sync_ret = regcache_default_sync(map, 0, map->max_register);
462
463 if (sync_ret == 0)
464 map->cache_dirty = false;
465
466out:
467 /* Restore the bypass state */
468 map->cache_bypass = bypass;
469 map->no_sync_defaults = false;
470
471 /*
472 * If we did any paging with cache bypassed and a cached
473 * paging register then the register and cache state might
474 * have gone out of sync, force writes of all the paging
475 * registers.
476 */
477 rb_for_each(node, NULL, &map->range_tree, rbtree_all) {
478 struct regmap_range_node *this =
479 rb_entry(node, struct regmap_range_node, node);
480
481 /* If there's nothing in the cache there's nothing to sync */
482 if (regcache_read(map, this->selector_reg, &i) != 0)
483 continue;
484
485 selector_ret = _regmap_write(map, this->selector_reg, i);
486 if (selector_ret != 0) {
487 map->cache_dirty = true;
488 dev_err(map->dev, "Failed to write %x = %x: %d\n",
489 this->selector_reg, i, selector_ret);
490 break;
491 }
492 }
493
494 map->unlock(map->lock_arg);
495
496 regmap_async_complete(map);
497
498 trace_regcache_sync(map, name, "stop");
499
500 return sync_ret ? sync_ret : selector_ret;
501}
502EXPORT_SYMBOL_GPL(regcache_sync);
503
504/**
505 * regcache_sync_region - Sync part of the register cache with the hardware.
506 *
507 * @map: map to sync.
508 * @min: first register to sync
509 * @max: last register to sync
510 *
511 * Write all non-default register values in the specified region to
512 * the hardware.
513 *
514 * Return a negative value on failure, 0 on success.
515 */
516int regcache_sync_region(struct regmap *map, unsigned int min,
517 unsigned int max)
518{
519 int ret = 0;
520 const char *name;
521 bool bypass;
522
523 if (WARN_ON(map->cache_type == REGCACHE_NONE))
524 return -EINVAL;
525
526 BUG_ON(!map->cache_ops);
527
528 map->lock(map->lock_arg);
529
530 if (WARN_ON(map->cache_only)) {
531 map->unlock(map->lock_arg);
532 return -EINVAL;
533 }
534 /* Remember the initial bypass state */
535 bypass = map->cache_bypass;
536
537 name = map->cache_ops->name;
538 dev_dbg(map->dev, "Syncing %s cache from %#x-%#x\n", name, min, max);
539
540 trace_regcache_sync(map, name, "start region");
541
542 if (!map->cache_dirty)
543 goto out;
544
545 map->async = true;
546
547 if (map->cache_ops->sync)
548 ret = map->cache_ops->sync(map, min, max);
549 else
550 ret = regcache_default_sync(map, min, max);
551
552out:
553 /* Restore the bypass state */
554 map->cache_bypass = bypass;
555 map->async = false;
556 map->no_sync_defaults = false;
557 map->unlock(map->lock_arg);
558
559 regmap_async_complete(map);
560
561 trace_regcache_sync(map, name, "stop region");
562
563 return ret;
564}
565EXPORT_SYMBOL_GPL(regcache_sync_region);
566
567/**
568 * regcache_drop_region - Discard part of the register cache
569 *
570 * @map: map to operate on
571 * @min: first register to discard
572 * @max: last register to discard
573 *
574 * Discard part of the register cache.
575 *
576 * Return a negative value on failure, 0 on success.
577 */
578int regcache_drop_region(struct regmap *map, unsigned int min,
579 unsigned int max)
580{
581 int ret = 0;
582
583 if (!map->cache_ops || !map->cache_ops->drop)
584 return -EINVAL;
585
586 map->lock(map->lock_arg);
587
588 trace_regcache_drop_region(map, min, max);
589
590 ret = map->cache_ops->drop(map, min, max);
591
592 map->unlock(map->lock_arg);
593
594 return ret;
595}
596EXPORT_SYMBOL_GPL(regcache_drop_region);
597
598/**
599 * regcache_cache_only - Put a register map into cache only mode
600 *
601 * @map: map to configure
602 * @enable: flag if changes should be written to the hardware
603 *
604 * When a register map is marked as cache only writes to the register
605 * map API will only update the register cache, they will not cause
606 * any hardware changes. This is useful for allowing portions of
607 * drivers to act as though the device were functioning as normal when
608 * it is disabled for power saving reasons.
609 */
610void regcache_cache_only(struct regmap *map, bool enable)
611{
612 map->lock(map->lock_arg);
613 WARN_ON(map->cache_type != REGCACHE_NONE &&
614 map->cache_bypass && enable);
615 map->cache_only = enable;
616 trace_regmap_cache_only(map, enable);
617 map->unlock(map->lock_arg);
618}
619EXPORT_SYMBOL_GPL(regcache_cache_only);
620
621/**
622 * regcache_mark_dirty - Indicate that HW registers were reset to default values
623 *
624 * @map: map to mark
625 *
626 * Inform regcache that the device has been powered down or reset, so that
627 * on resume, regcache_sync() knows to write out all non-default values
628 * stored in the cache.
629 *
630 * If this function is not called, regcache_sync() will assume that
631 * the hardware state still matches the cache state, modulo any writes that
632 * happened when cache_only was true.
633 */
634void regcache_mark_dirty(struct regmap *map)
635{
636 map->lock(map->lock_arg);
637 map->cache_dirty = true;
638 map->no_sync_defaults = true;
639 map->unlock(map->lock_arg);
640}
641EXPORT_SYMBOL_GPL(regcache_mark_dirty);
642
643/**
644 * regcache_cache_bypass - Put a register map into cache bypass mode
645 *
646 * @map: map to configure
647 * @enable: flag if changes should not be written to the cache
648 *
649 * When a register map is marked with the cache bypass option, writes
650 * to the register map API will only update the hardware and not
651 * the cache directly. This is useful when syncing the cache back to
652 * the hardware.
653 */
654void regcache_cache_bypass(struct regmap *map, bool enable)
655{
656 map->lock(map->lock_arg);
657 WARN_ON(map->cache_only && enable);
658 map->cache_bypass = enable;
659 trace_regmap_cache_bypass(map, enable);
660 map->unlock(map->lock_arg);
661}
662EXPORT_SYMBOL_GPL(regcache_cache_bypass);
663
664/**
665 * regcache_reg_cached - Check if a register is cached
666 *
667 * @map: map to check
668 * @reg: register to check
669 *
670 * Reports if a register is cached.
671 */
672bool regcache_reg_cached(struct regmap *map, unsigned int reg)
673{
674 unsigned int val;
675 int ret;
676
677 map->lock(map->lock_arg);
678
679 ret = regcache_read(map, reg, &val);
680
681 map->unlock(map->lock_arg);
682
683 return ret == 0;
684}
685EXPORT_SYMBOL_GPL(regcache_reg_cached);
686
687void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
688 unsigned int val)
689{
690 /* Use device native format if possible */
691 if (map->format.format_val) {
692 map->format.format_val(base + (map->cache_word_size * idx),
693 val, 0);
694 return;
695 }
696
697 switch (map->cache_word_size) {
698 case 1: {
699 u8 *cache = base;
700
701 cache[idx] = val;
702 break;
703 }
704 case 2: {
705 u16 *cache = base;
706
707 cache[idx] = val;
708 break;
709 }
710 case 4: {
711 u32 *cache = base;
712
713 cache[idx] = val;
714 break;
715 }
716 default:
717 BUG();
718 }
719}
720
721unsigned int regcache_get_val(struct regmap *map, const void *base,
722 unsigned int idx)
723{
724 if (!base)
725 return -EINVAL;
726
727 /* Use device native format if possible */
728 if (map->format.parse_val)
729 return map->format.parse_val(regcache_get_val_addr(map, base,
730 idx));
731
732 switch (map->cache_word_size) {
733 case 1: {
734 const u8 *cache = base;
735
736 return cache[idx];
737 }
738 case 2: {
739 const u16 *cache = base;
740
741 return cache[idx];
742 }
743 case 4: {
744 const u32 *cache = base;
745
746 return cache[idx];
747 }
748 default:
749 BUG();
750 }
751 /* unreachable */
752 return -1;
753}
754
755int regcache_lookup_reg(struct regmap *map, unsigned int reg)
756{
757 struct reg_default key;
758 struct reg_default *r;
759
760 key.reg = reg;
761 key.def = 0;
762
763 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
764 sizeof(struct reg_default), regcache_defaults_cmp);
765
766 if (r)
767 return r - map->reg_defaults;
768 else
769 return -ENOENT;
770}
771
772static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
773{
774 if (!cache_present)
775 return true;
776
777 return test_bit(idx, cache_present);
778}
779
780int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
781{
782 int ret;
783
784 if (!regcache_reg_needs_sync(map, reg, val))
785 return 0;
786
787 map->cache_bypass = true;
788
789 ret = _regmap_write(map, reg, val);
790
791 map->cache_bypass = false;
792
793 if (ret != 0) {
794 dev_err(map->dev, "Unable to sync register %#x. %d\n",
795 reg, ret);
796 return ret;
797 }
798 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
799 reg, val);
800
801 return 0;
802}
803
804static int regcache_sync_block_single(struct regmap *map, void *block,
805 unsigned long *cache_present,
806 unsigned int block_base,
807 unsigned int start, unsigned int end)
808{
809 unsigned int i, regtmp, val;
810 int ret;
811
812 for (i = start; i < end; i++) {
813 regtmp = block_base + (i * map->reg_stride);
814
815 if (!regcache_reg_present(cache_present, i) ||
816 !regmap_writeable(map, regtmp))
817 continue;
818
819 val = regcache_get_val(map, block, i);
820 ret = regcache_sync_val(map, regtmp, val);
821 if (ret != 0)
822 return ret;
823 }
824
825 return 0;
826}
827
828static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
829 unsigned int base, unsigned int cur)
830{
831 size_t val_bytes = map->format.val_bytes;
832 int ret, count;
833
834 if (*data == NULL)
835 return 0;
836
837 count = (cur - base) / map->reg_stride;
838
839 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
840 count * val_bytes, count, base, cur - map->reg_stride);
841
842 map->cache_bypass = true;
843
844 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
845 if (ret)
846 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
847 base, cur - map->reg_stride, ret);
848
849 map->cache_bypass = false;
850
851 *data = NULL;
852
853 return ret;
854}
855
856static int regcache_sync_block_raw(struct regmap *map, void *block,
857 unsigned long *cache_present,
858 unsigned int block_base, unsigned int start,
859 unsigned int end)
860{
861 unsigned int regtmp = 0;
862 unsigned int base = 0;
863 const void *data = NULL;
864 unsigned int val;
865 int ret;
866
867 for (unsigned int i = start; i < end; i++) {
868 regtmp = block_base + (i * map->reg_stride);
869
870 if (!regcache_reg_present(cache_present, i) ||
871 !regmap_writeable(map, regtmp)) {
872 ret = regcache_sync_block_raw_flush(map, &data,
873 base, regtmp);
874 if (ret != 0)
875 return ret;
876 continue;
877 }
878
879 val = regcache_get_val(map, block, i);
880 if (!regcache_reg_needs_sync(map, regtmp, val)) {
881 ret = regcache_sync_block_raw_flush(map, &data,
882 base, regtmp);
883 if (ret != 0)
884 return ret;
885 continue;
886 }
887
888 if (!data) {
889 data = regcache_get_val_addr(map, block, i);
890 base = regtmp;
891 }
892 }
893
894 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
895 map->reg_stride);
896}
897
898int regcache_sync_block(struct regmap *map, void *block,
899 unsigned long *cache_present,
900 unsigned int block_base, unsigned int start,
901 unsigned int end)
902{
903 if (regmap_can_raw_write(map) && !map->use_single_write)
904 return regcache_sync_block_raw(map, block, cache_present,
905 block_base, start, end);
906 else
907 return regcache_sync_block_single(map, block, cache_present,
908 block_base, start, end);
909}