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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/clocksource/arm_arch_timer.c
4 *
5 * Copyright (C) 2011 ARM Ltd.
6 * All Rights Reserved
7 */
8
9#define pr_fmt(fmt) "arch_timer: " fmt
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/device.h>
14#include <linux/smp.h>
15#include <linux/cpu.h>
16#include <linux/cpu_pm.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/clocksource_ids.h>
20#include <linux/interrupt.h>
21#include <linux/kstrtox.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/sched/clock.h>
27#include <linux/sched_clock.h>
28#include <linux/acpi.h>
29#include <linux/arm-smccc.h>
30#include <linux/ptp_kvm.h>
31
32#include <asm/arch_timer.h>
33#include <asm/virt.h>
34
35#include <clocksource/arm_arch_timer.h>
36
37/*
38 * The minimum amount of time a generic counter is guaranteed to not roll over
39 * (40 years)
40 */
41#define MIN_ROLLOVER_SECS (40ULL * 365 * 24 * 3600)
42
43static u32 arch_timer_rate __ro_after_init;
44static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
45
46static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
47 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
48 [ARCH_TIMER_PHYS_NONSECURE_PPI] = "phys",
49 [ARCH_TIMER_VIRT_PPI] = "virt",
50 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
51 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
52};
53
54static struct clock_event_device __percpu *arch_timer_evt;
55
56static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI;
57static bool arch_timer_c3stop __ro_after_init;
58static bool arch_counter_suspend_stop __ro_after_init;
59static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
60
61static cpumask_t evtstrm_available = CPU_MASK_NONE;
62static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
63
64static int __init early_evtstrm_cfg(char *buf)
65{
66 return kstrtobool(buf, &evtstrm_enable);
67}
68early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
69
70/*
71 * Makes an educated guess at a valid counter width based on the Generic Timer
72 * specification. Of note:
73 * 1) the system counter is at least 56 bits wide
74 * 2) a roll-over time of not less than 40 years
75 *
76 * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
77 */
78static int arch_counter_get_width(void)
79{
80 u64 min_cycles = MIN_ROLLOVER_SECS * arch_timer_rate;
81
82 /* guarantee the returned width is within the valid range */
83 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64);
84}
85
86/*
87 * Architected system timer support.
88 */
89static noinstr u64 raw_counter_get_cntpct_stable(void)
90{
91 return __arch_counter_get_cntpct_stable();
92}
93
94static notrace u64 arch_counter_get_cntpct_stable(void)
95{
96 u64 val;
97 preempt_disable_notrace();
98 val = __arch_counter_get_cntpct_stable();
99 preempt_enable_notrace();
100 return val;
101}
102
103static noinstr u64 arch_counter_get_cntpct(void)
104{
105 return __arch_counter_get_cntpct();
106}
107
108static noinstr u64 raw_counter_get_cntvct_stable(void)
109{
110 return __arch_counter_get_cntvct_stable();
111}
112
113static notrace u64 arch_counter_get_cntvct_stable(void)
114{
115 u64 val;
116 preempt_disable_notrace();
117 val = __arch_counter_get_cntvct_stable();
118 preempt_enable_notrace();
119 return val;
120}
121
122static noinstr u64 arch_counter_get_cntvct(void)
123{
124 return __arch_counter_get_cntvct();
125}
126
127/*
128 * Default to cp15 based access because arm64 uses this function for
129 * sched_clock() before DT is probed and the cp15 method is guaranteed
130 * to exist on arm64. arm doesn't use this before DT is probed so even
131 * if we don't have the cp15 accessors we won't have a problem.
132 */
133u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct;
134EXPORT_SYMBOL_GPL(arch_timer_read_counter);
135
136static u64 arch_counter_read(struct clocksource *cs)
137{
138 return arch_timer_read_counter();
139}
140
141static u64 arch_counter_read_cc(struct cyclecounter *cc)
142{
143 return arch_timer_read_counter();
144}
145
146static struct clocksource clocksource_counter = {
147 .name = "arch_sys_counter",
148 .id = CSID_ARM_ARCH_COUNTER,
149 .rating = 400,
150 .read = arch_counter_read,
151 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
152};
153
154static struct cyclecounter cyclecounter __ro_after_init = {
155 .read = arch_counter_read_cc,
156};
157
158struct ate_acpi_oem_info {
159 char oem_id[ACPI_OEM_ID_SIZE + 1];
160 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
161 u32 oem_revision;
162};
163
164#ifdef CONFIG_FSL_ERRATUM_A008585
165/*
166 * The number of retries is an arbitrary value well beyond the highest number
167 * of iterations the loop has been observed to take.
168 */
169#define __fsl_a008585_read_reg(reg) ({ \
170 u64 _old, _new; \
171 int _retries = 200; \
172 \
173 do { \
174 _old = read_sysreg(reg); \
175 _new = read_sysreg(reg); \
176 _retries--; \
177 } while (unlikely(_old != _new) && _retries); \
178 \
179 WARN_ON_ONCE(!_retries); \
180 _new; \
181})
182
183static u64 notrace fsl_a008585_read_cntpct_el0(void)
184{
185 return __fsl_a008585_read_reg(cntpct_el0);
186}
187
188static u64 notrace fsl_a008585_read_cntvct_el0(void)
189{
190 return __fsl_a008585_read_reg(cntvct_el0);
191}
192#endif
193
194#ifdef CONFIG_HISILICON_ERRATUM_161010101
195/*
196 * Verify whether the value of the second read is larger than the first by
197 * less than 32 is the only way to confirm the value is correct, so clear the
198 * lower 5 bits to check whether the difference is greater than 32 or not.
199 * Theoretically the erratum should not occur more than twice in succession
200 * when reading the system counter, but it is possible that some interrupts
201 * may lead to more than twice read errors, triggering the warning, so setting
202 * the number of retries far beyond the number of iterations the loop has been
203 * observed to take.
204 */
205#define __hisi_161010101_read_reg(reg) ({ \
206 u64 _old, _new; \
207 int _retries = 50; \
208 \
209 do { \
210 _old = read_sysreg(reg); \
211 _new = read_sysreg(reg); \
212 _retries--; \
213 } while (unlikely((_new - _old) >> 5) && _retries); \
214 \
215 WARN_ON_ONCE(!_retries); \
216 _new; \
217})
218
219static u64 notrace hisi_161010101_read_cntpct_el0(void)
220{
221 return __hisi_161010101_read_reg(cntpct_el0);
222}
223
224static u64 notrace hisi_161010101_read_cntvct_el0(void)
225{
226 return __hisi_161010101_read_reg(cntvct_el0);
227}
228
229static const struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
230 /*
231 * Note that trailing spaces are required to properly match
232 * the OEM table information.
233 */
234 {
235 .oem_id = "HISI ",
236 .oem_table_id = "HIP05 ",
237 .oem_revision = 0,
238 },
239 {
240 .oem_id = "HISI ",
241 .oem_table_id = "HIP06 ",
242 .oem_revision = 0,
243 },
244 {
245 .oem_id = "HISI ",
246 .oem_table_id = "HIP07 ",
247 .oem_revision = 0,
248 },
249 { /* Sentinel indicating the end of the OEM array */ },
250};
251#endif
252
253#ifdef CONFIG_ARM64_ERRATUM_858921
254static u64 notrace arm64_858921_read_cntpct_el0(void)
255{
256 u64 old, new;
257
258 old = read_sysreg(cntpct_el0);
259 new = read_sysreg(cntpct_el0);
260 return (((old ^ new) >> 32) & 1) ? old : new;
261}
262
263static u64 notrace arm64_858921_read_cntvct_el0(void)
264{
265 u64 old, new;
266
267 old = read_sysreg(cntvct_el0);
268 new = read_sysreg(cntvct_el0);
269 return (((old ^ new) >> 32) & 1) ? old : new;
270}
271#endif
272
273#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
274/*
275 * The low bits of the counter registers are indeterminate while bit 10 or
276 * greater is rolling over. Since the counter value can jump both backward
277 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
278 * with all ones or all zeros in the low bits. Bound the loop by the maximum
279 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
280 */
281#define __sun50i_a64_read_reg(reg) ({ \
282 u64 _val; \
283 int _retries = 150; \
284 \
285 do { \
286 _val = read_sysreg(reg); \
287 _retries--; \
288 } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \
289 \
290 WARN_ON_ONCE(!_retries); \
291 _val; \
292})
293
294static u64 notrace sun50i_a64_read_cntpct_el0(void)
295{
296 return __sun50i_a64_read_reg(cntpct_el0);
297}
298
299static u64 notrace sun50i_a64_read_cntvct_el0(void)
300{
301 return __sun50i_a64_read_reg(cntvct_el0);
302}
303#endif
304
305#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
306DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
307EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
308
309static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
310
311/*
312 * Force the inlining of this function so that the register accesses
313 * can be themselves correctly inlined.
314 */
315static __always_inline
316void erratum_set_next_event_generic(const int access, unsigned long evt,
317 struct clock_event_device *clk)
318{
319 unsigned long ctrl;
320 u64 cval;
321
322 ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL);
323 ctrl |= ARCH_TIMER_CTRL_ENABLE;
324 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
325
326 if (access == ARCH_TIMER_PHYS_ACCESS) {
327 cval = evt + arch_counter_get_cntpct_stable();
328 write_sysreg(cval, cntp_cval_el0);
329 } else {
330 cval = evt + arch_counter_get_cntvct_stable();
331 write_sysreg(cval, cntv_cval_el0);
332 }
333
334 arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl);
335}
336
337static __maybe_unused int erratum_set_next_event_virt(unsigned long evt,
338 struct clock_event_device *clk)
339{
340 erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
341 return 0;
342}
343
344static __maybe_unused int erratum_set_next_event_phys(unsigned long evt,
345 struct clock_event_device *clk)
346{
347 erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
348 return 0;
349}
350
351static const struct arch_timer_erratum_workaround ool_workarounds[] = {
352#ifdef CONFIG_FSL_ERRATUM_A008585
353 {
354 .match_type = ate_match_dt,
355 .id = "fsl,erratum-a008585",
356 .desc = "Freescale erratum a005858",
357 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
358 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
359 .set_next_event_phys = erratum_set_next_event_phys,
360 .set_next_event_virt = erratum_set_next_event_virt,
361 },
362#endif
363#ifdef CONFIG_HISILICON_ERRATUM_161010101
364 {
365 .match_type = ate_match_dt,
366 .id = "hisilicon,erratum-161010101",
367 .desc = "HiSilicon erratum 161010101",
368 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
369 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
370 .set_next_event_phys = erratum_set_next_event_phys,
371 .set_next_event_virt = erratum_set_next_event_virt,
372 },
373 {
374 .match_type = ate_match_acpi_oem_info,
375 .id = hisi_161010101_oem_info,
376 .desc = "HiSilicon erratum 161010101",
377 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
378 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
379 .set_next_event_phys = erratum_set_next_event_phys,
380 .set_next_event_virt = erratum_set_next_event_virt,
381 },
382#endif
383#ifdef CONFIG_ARM64_ERRATUM_858921
384 {
385 .match_type = ate_match_local_cap_id,
386 .id = (void *)ARM64_WORKAROUND_858921,
387 .desc = "ARM erratum 858921",
388 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
389 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
390 .set_next_event_phys = erratum_set_next_event_phys,
391 .set_next_event_virt = erratum_set_next_event_virt,
392 },
393#endif
394#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
395 {
396 .match_type = ate_match_dt,
397 .id = "allwinner,erratum-unknown1",
398 .desc = "Allwinner erratum UNKNOWN1",
399 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
400 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
401 .set_next_event_phys = erratum_set_next_event_phys,
402 .set_next_event_virt = erratum_set_next_event_virt,
403 },
404#endif
405#ifdef CONFIG_ARM64_ERRATUM_1418040
406 {
407 .match_type = ate_match_local_cap_id,
408 .id = (void *)ARM64_WORKAROUND_1418040,
409 .desc = "ARM erratum 1418040",
410 .disable_compat_vdso = true,
411 },
412#endif
413};
414
415typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
416 const void *);
417
418static
419bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
420 const void *arg)
421{
422 const struct device_node *np = arg;
423
424 return of_property_read_bool(np, wa->id);
425}
426
427static
428bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
429 const void *arg)
430{
431 return this_cpu_has_cap((uintptr_t)wa->id);
432}
433
434
435static
436bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
437 const void *arg)
438{
439 static const struct ate_acpi_oem_info empty_oem_info = {};
440 const struct ate_acpi_oem_info *info = wa->id;
441 const struct acpi_table_header *table = arg;
442
443 /* Iterate over the ACPI OEM info array, looking for a match */
444 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
445 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
446 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
447 info->oem_revision == table->oem_revision)
448 return true;
449
450 info++;
451 }
452
453 return false;
454}
455
456static const struct arch_timer_erratum_workaround *
457arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
458 ate_match_fn_t match_fn,
459 void *arg)
460{
461 int i;
462
463 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
464 if (ool_workarounds[i].match_type != type)
465 continue;
466
467 if (match_fn(&ool_workarounds[i], arg))
468 return &ool_workarounds[i];
469 }
470
471 return NULL;
472}
473
474static
475void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
476 bool local)
477{
478 int i;
479
480 if (local) {
481 __this_cpu_write(timer_unstable_counter_workaround, wa);
482 } else {
483 for_each_possible_cpu(i)
484 per_cpu(timer_unstable_counter_workaround, i) = wa;
485 }
486
487 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
488 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
489
490 /*
491 * Don't use the vdso fastpath if errata require using the
492 * out-of-line counter accessor. We may change our mind pretty
493 * late in the game (with a per-CPU erratum, for example), so
494 * change both the default value and the vdso itself.
495 */
496 if (wa->read_cntvct_el0) {
497 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
498 vdso_default = VDSO_CLOCKMODE_NONE;
499 } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
500 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
501 clocksource_counter.vdso_clock_mode = vdso_default;
502 }
503}
504
505static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
506 void *arg)
507{
508 const struct arch_timer_erratum_workaround *wa, *__wa;
509 ate_match_fn_t match_fn = NULL;
510 bool local = false;
511
512 switch (type) {
513 case ate_match_dt:
514 match_fn = arch_timer_check_dt_erratum;
515 break;
516 case ate_match_local_cap_id:
517 match_fn = arch_timer_check_local_cap_erratum;
518 local = true;
519 break;
520 case ate_match_acpi_oem_info:
521 match_fn = arch_timer_check_acpi_oem_erratum;
522 break;
523 default:
524 WARN_ON(1);
525 return;
526 }
527
528 wa = arch_timer_iterate_errata(type, match_fn, arg);
529 if (!wa)
530 return;
531
532 __wa = __this_cpu_read(timer_unstable_counter_workaround);
533 if (__wa && wa != __wa)
534 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
535 wa->desc, __wa->desc);
536
537 if (__wa)
538 return;
539
540 arch_timer_enable_workaround(wa, local);
541 pr_info("Enabling %s workaround for %s\n",
542 local ? "local" : "global", wa->desc);
543}
544
545static bool arch_timer_this_cpu_has_cntvct_wa(void)
546{
547 return has_erratum_handler(read_cntvct_el0);
548}
549
550static bool arch_timer_counter_has_wa(void)
551{
552 return atomic_read(&timer_unstable_counter_workaround_in_use);
553}
554#else
555#define arch_timer_check_ool_workaround(t,a) do { } while(0)
556#define arch_timer_this_cpu_has_cntvct_wa() ({false;})
557#define arch_timer_counter_has_wa() ({false;})
558#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
559
560static __always_inline irqreturn_t timer_handler(const int access,
561 struct clock_event_device *evt)
562{
563 unsigned long ctrl;
564
565 ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL);
566 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
567 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
568 arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl);
569 evt->event_handler(evt);
570 return IRQ_HANDLED;
571 }
572
573 return IRQ_NONE;
574}
575
576static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
577{
578 struct clock_event_device *evt = dev_id;
579
580 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
581}
582
583static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
584{
585 struct clock_event_device *evt = dev_id;
586
587 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
588}
589
590static __always_inline int arch_timer_shutdown(const int access,
591 struct clock_event_device *clk)
592{
593 unsigned long ctrl;
594
595 ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL);
596 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
597 arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl);
598
599 return 0;
600}
601
602static int arch_timer_shutdown_virt(struct clock_event_device *clk)
603{
604 return arch_timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
605}
606
607static int arch_timer_shutdown_phys(struct clock_event_device *clk)
608{
609 return arch_timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
610}
611
612static __always_inline void set_next_event(const int access, unsigned long evt,
613 struct clock_event_device *clk)
614{
615 unsigned long ctrl;
616 u64 cnt;
617
618 ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL);
619 ctrl |= ARCH_TIMER_CTRL_ENABLE;
620 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
621
622 if (access == ARCH_TIMER_PHYS_ACCESS)
623 cnt = __arch_counter_get_cntpct();
624 else
625 cnt = __arch_counter_get_cntvct();
626
627 arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CVAL, evt + cnt);
628 arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl);
629}
630
631static int arch_timer_set_next_event_virt(unsigned long evt,
632 struct clock_event_device *clk)
633{
634 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
635 return 0;
636}
637
638static int arch_timer_set_next_event_phys(unsigned long evt,
639 struct clock_event_device *clk)
640{
641 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
642 return 0;
643}
644
645static u64 __arch_timer_check_delta(void)
646{
647#ifdef CONFIG_ARM64
648 const struct midr_range broken_cval_midrs[] = {
649 /*
650 * XGene-1 implements CVAL in terms of TVAL, meaning
651 * that the maximum timer range is 32bit. Shame on them.
652 *
653 * Note that TVAL is signed, thus has only 31 of its
654 * 32 bits to express magnitude.
655 */
656 MIDR_REV_RANGE(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
657 APM_CPU_PART_XGENE),
658 APM_CPU_VAR_POTENZA, 0x0, 0xf),
659 {},
660 };
661
662 if (is_midr_in_range_list(broken_cval_midrs)) {
663 pr_warn_once("Broken CNTx_CVAL_EL1, using 31 bit TVAL instead.\n");
664 return CLOCKSOURCE_MASK(31);
665 }
666#endif
667 return CLOCKSOURCE_MASK(arch_counter_get_width());
668}
669
670static void __arch_timer_setup(struct clock_event_device *clk)
671{
672 typeof(clk->set_next_event) sne;
673 u64 max_delta;
674
675 clk->features = CLOCK_EVT_FEAT_ONESHOT;
676
677 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
678
679 if (arch_timer_c3stop)
680 clk->features |= CLOCK_EVT_FEAT_C3STOP;
681 clk->name = "arch_sys_timer";
682 clk->rating = 450;
683 clk->cpumask = cpumask_of(smp_processor_id());
684 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
685 switch (arch_timer_uses_ppi) {
686 case ARCH_TIMER_VIRT_PPI:
687 case ARCH_TIMER_HYP_VIRT_PPI:
688 clk->set_state_shutdown = arch_timer_shutdown_virt;
689 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
690 sne = erratum_handler(set_next_event_virt);
691 break;
692 case ARCH_TIMER_PHYS_SECURE_PPI:
693 case ARCH_TIMER_PHYS_NONSECURE_PPI:
694 case ARCH_TIMER_HYP_PPI:
695 clk->set_state_shutdown = arch_timer_shutdown_phys;
696 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
697 sne = erratum_handler(set_next_event_phys);
698 break;
699 default:
700 BUG();
701 }
702
703 clk->set_next_event = sne;
704 max_delta = __arch_timer_check_delta();
705
706 clk->set_state_shutdown(clk);
707
708 clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
709}
710
711static void arch_timer_evtstrm_enable(unsigned int divider)
712{
713 u32 cntkctl = arch_timer_get_cntkctl();
714
715#ifdef CONFIG_ARM64
716 /* ECV is likely to require a large divider. Use the EVNTIS flag. */
717 if (cpus_have_final_cap(ARM64_HAS_ECV) && divider > 15) {
718 cntkctl |= ARCH_TIMER_EVT_INTERVAL_SCALE;
719 divider -= 8;
720 }
721#endif
722
723 divider = min(divider, 15U);
724 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
725 /* Set the divider and enable virtual event stream */
726 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
727 | ARCH_TIMER_VIRT_EVT_EN;
728 arch_timer_set_cntkctl(cntkctl);
729 arch_timer_set_evtstrm_feature();
730 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
731}
732
733static void arch_timer_configure_evtstream(void)
734{
735 int evt_stream_div, lsb;
736
737 /*
738 * As the event stream can at most be generated at half the frequency
739 * of the counter, use half the frequency when computing the divider.
740 */
741 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
742
743 /*
744 * Find the closest power of two to the divisor. If the adjacent bit
745 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
746 */
747 lsb = fls(evt_stream_div) - 1;
748 if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
749 lsb++;
750
751 /* enable event stream */
752 arch_timer_evtstrm_enable(max(0, lsb));
753}
754
755static int arch_timer_evtstrm_starting_cpu(unsigned int cpu)
756{
757 arch_timer_configure_evtstream();
758 return 0;
759}
760
761static int arch_timer_evtstrm_dying_cpu(unsigned int cpu)
762{
763 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
764 return 0;
765}
766
767static int __init arch_timer_evtstrm_register(void)
768{
769 if (!arch_timer_evt || !evtstrm_enable)
770 return 0;
771
772 return cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING,
773 "clockevents/arm/arch_timer_evtstrm:starting",
774 arch_timer_evtstrm_starting_cpu,
775 arch_timer_evtstrm_dying_cpu);
776}
777core_initcall(arch_timer_evtstrm_register);
778
779static void arch_counter_set_user_access(void)
780{
781 u32 cntkctl = arch_timer_get_cntkctl();
782
783 /* Disable user access to the timers and both counters */
784 /* Also disable virtual event stream */
785 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
786 | ARCH_TIMER_USR_VT_ACCESS_EN
787 | ARCH_TIMER_USR_VCT_ACCESS_EN
788 | ARCH_TIMER_VIRT_EVT_EN
789 | ARCH_TIMER_USR_PCT_ACCESS_EN);
790
791 /*
792 * Enable user access to the virtual counter if it doesn't
793 * need to be workaround. The vdso may have been already
794 * disabled though.
795 */
796 if (arch_timer_this_cpu_has_cntvct_wa())
797 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
798 else
799 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
800
801 arch_timer_set_cntkctl(cntkctl);
802}
803
804static bool arch_timer_has_nonsecure_ppi(void)
805{
806 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
807 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
808}
809
810static u32 check_ppi_trigger(int irq)
811{
812 u32 flags = irq_get_trigger_type(irq);
813
814 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
815 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
816 pr_warn("WARNING: Please fix your firmware\n");
817 flags = IRQF_TRIGGER_LOW;
818 }
819
820 return flags;
821}
822
823static int arch_timer_starting_cpu(unsigned int cpu)
824{
825 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
826 u32 flags;
827
828 __arch_timer_setup(clk);
829
830 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
831 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
832
833 if (arch_timer_has_nonsecure_ppi()) {
834 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
835 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
836 flags);
837 }
838
839 arch_counter_set_user_access();
840
841 return 0;
842}
843
844static int validate_timer_rate(void)
845{
846 if (!arch_timer_rate)
847 return -EINVAL;
848
849 /* Arch timer frequency < 1MHz can cause trouble */
850 WARN_ON(arch_timer_rate < 1000000);
851
852 return 0;
853}
854
855/*
856 * For historical reasons, when probing with DT we use whichever (non-zero)
857 * rate was probed first, and don't verify that others match. If the first node
858 * probed has a clock-frequency property, this overrides the HW register.
859 */
860static void __init arch_timer_of_configure_rate(u32 rate, struct device_node *np)
861{
862 /* Who has more than one independent system counter? */
863 if (arch_timer_rate)
864 return;
865
866 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
867 arch_timer_rate = rate;
868
869 /* Check the timer frequency. */
870 if (validate_timer_rate())
871 pr_warn("frequency not available\n");
872}
873
874static void __init arch_timer_banner(void)
875{
876 pr_info("cp15 timer running at %lu.%02luMHz (%s).\n",
877 (unsigned long)arch_timer_rate / 1000000,
878 (unsigned long)(arch_timer_rate / 10000) % 100,
879 arch_timer_ppi_names[arch_timer_uses_ppi]);
880}
881
882u32 arch_timer_get_rate(void)
883{
884 return arch_timer_rate;
885}
886
887bool arch_timer_evtstrm_available(void)
888{
889 /*
890 * We might get called from a preemptible context. This is fine
891 * because availability of the event stream should be always the same
892 * for a preemptible context and context where we might resume a task.
893 */
894 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
895}
896
897static struct arch_timer_kvm_info arch_timer_kvm_info;
898
899struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
900{
901 return &arch_timer_kvm_info;
902}
903
904static void __init arch_counter_register(void)
905{
906 u64 (*scr)(void);
907 u64 (*rd)(void);
908 u64 start_count;
909 int width;
910
911 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
912 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI ||
913 arch_timer_uses_ppi == ARCH_TIMER_HYP_VIRT_PPI) {
914 if (arch_timer_counter_has_wa()) {
915 rd = arch_counter_get_cntvct_stable;
916 scr = raw_counter_get_cntvct_stable;
917 } else {
918 rd = arch_counter_get_cntvct;
919 scr = arch_counter_get_cntvct;
920 }
921 } else {
922 if (arch_timer_counter_has_wa()) {
923 rd = arch_counter_get_cntpct_stable;
924 scr = raw_counter_get_cntpct_stable;
925 } else {
926 rd = arch_counter_get_cntpct;
927 scr = arch_counter_get_cntpct;
928 }
929 }
930
931 arch_timer_read_counter = rd;
932 clocksource_counter.vdso_clock_mode = vdso_default;
933
934 width = arch_counter_get_width();
935 clocksource_counter.mask = CLOCKSOURCE_MASK(width);
936 cyclecounter.mask = CLOCKSOURCE_MASK(width);
937
938 if (!arch_counter_suspend_stop)
939 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
940 start_count = arch_timer_read_counter();
941 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
942 cyclecounter.mult = clocksource_counter.mult;
943 cyclecounter.shift = clocksource_counter.shift;
944 timecounter_init(&arch_timer_kvm_info.timecounter,
945 &cyclecounter, start_count);
946
947 sched_clock_register(scr, width, arch_timer_rate);
948}
949
950static void arch_timer_stop(struct clock_event_device *clk)
951{
952 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
953
954 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
955 if (arch_timer_has_nonsecure_ppi())
956 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
957}
958
959static int arch_timer_dying_cpu(unsigned int cpu)
960{
961 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
962
963 arch_timer_stop(clk);
964 return 0;
965}
966
967#ifdef CONFIG_CPU_PM
968static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
969static int arch_timer_cpu_pm_notify(struct notifier_block *self,
970 unsigned long action, void *hcpu)
971{
972 if (action == CPU_PM_ENTER) {
973 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
974
975 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
976 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
977 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
978
979 if (arch_timer_have_evtstrm_feature())
980 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
981 }
982 return NOTIFY_OK;
983}
984
985static struct notifier_block arch_timer_cpu_pm_notifier = {
986 .notifier_call = arch_timer_cpu_pm_notify,
987};
988
989static int __init arch_timer_cpu_pm_init(void)
990{
991 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
992}
993
994static void __init arch_timer_cpu_pm_deinit(void)
995{
996 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
997}
998
999#else
1000static int __init arch_timer_cpu_pm_init(void)
1001{
1002 return 0;
1003}
1004
1005static void __init arch_timer_cpu_pm_deinit(void)
1006{
1007}
1008#endif
1009
1010static int __init arch_timer_register(void)
1011{
1012 int err;
1013 int ppi;
1014
1015 arch_timer_evt = alloc_percpu(struct clock_event_device);
1016 if (!arch_timer_evt) {
1017 err = -ENOMEM;
1018 goto out;
1019 }
1020
1021 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1022 switch (arch_timer_uses_ppi) {
1023 case ARCH_TIMER_VIRT_PPI:
1024 case ARCH_TIMER_HYP_VIRT_PPI:
1025 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1026 "arch_timer", arch_timer_evt);
1027 break;
1028 case ARCH_TIMER_PHYS_SECURE_PPI:
1029 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1030 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1031 "arch_timer", arch_timer_evt);
1032 if (!err && arch_timer_has_nonsecure_ppi()) {
1033 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1034 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1035 "arch_timer", arch_timer_evt);
1036 if (err)
1037 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1038 arch_timer_evt);
1039 }
1040 break;
1041 case ARCH_TIMER_HYP_PPI:
1042 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1043 "arch_timer", arch_timer_evt);
1044 break;
1045 default:
1046 BUG();
1047 }
1048
1049 if (err) {
1050 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1051 goto out_free;
1052 }
1053
1054 err = arch_timer_cpu_pm_init();
1055 if (err)
1056 goto out_unreg_notify;
1057
1058 /* Register and immediately configure the timer on the boot CPU */
1059 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1060 "clockevents/arm/arch_timer:starting",
1061 arch_timer_starting_cpu, arch_timer_dying_cpu);
1062 if (err)
1063 goto out_unreg_cpupm;
1064 return 0;
1065
1066out_unreg_cpupm:
1067 arch_timer_cpu_pm_deinit();
1068
1069out_unreg_notify:
1070 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1071 if (arch_timer_has_nonsecure_ppi())
1072 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1073 arch_timer_evt);
1074
1075out_free:
1076 free_percpu(arch_timer_evt);
1077 arch_timer_evt = NULL;
1078out:
1079 return err;
1080}
1081
1082static int __init arch_timer_common_init(void)
1083{
1084 arch_timer_banner();
1085 arch_counter_register();
1086 return arch_timer_arch_init();
1087}
1088
1089static bool __init has_broken_el2_vtimer(void)
1090{
1091 /*
1092 * SoCs described here have been found to be broken, though no
1093 * explanation has been volunteered by the vendor. Let the user know
1094 * we're papering over the vendor's lack of communication.
1095 */
1096 static const char * const broken_el2_vtimer[] __initconst = {
1097 "brcm,bcm2712",
1098 NULL
1099 };
1100
1101 if (of_machine_compatible_match(broken_el2_vtimer)) {
1102 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1103 pr_warn_once(HW_ERR "Known broken EL2 virtual timer, ignoring it\n");
1104 return true;
1105 }
1106
1107 return false;
1108}
1109
1110/**
1111 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1112 *
1113 * On AArch32, if HYP mode is available, we know that the physical
1114 * timer has been configured to be accessible from PL1. Use it, so
1115 * that a guest can use the virtual timer instead (though KVM host
1116 * support has long been removed).
1117 *
1118 * On ARMv8.1 with FEAT_VHE, the kernel runs in EL2. Accesses to
1119 * CNTV_*_EL1 registers are silently redirected to their CNTHV_*_EL2
1120 * counterparts, and the timer uses a different PPI number. Similar
1121 * thing happen when using the EL2 physical timer. Note that a bunch
1122 * of DTs out there omit the virtual EL2 timer, so fallback gracefully
1123 * on the physical timer.
1124 *
1125 * Without VHE, if no interrupt provided for virtual timer, we'll have
1126 * to stick to the physical timer. It'd better be accessible...
1127 *
1128 * For arm64 we never use the secure interrupt.
1129 *
1130 * Return: a suitable PPI type for the current system.
1131 */
1132static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1133{
1134 if (is_kernel_in_hyp_mode()) {
1135 if (arch_timer_ppi[ARCH_TIMER_HYP_VIRT_PPI] &&
1136 !has_broken_el2_vtimer())
1137 return ARCH_TIMER_HYP_VIRT_PPI;
1138
1139 pr_warn_once(FW_BUG "VHE-capable CPU without EL2 virtual timer interrupt\n");
1140 return ARCH_TIMER_HYP_PPI;
1141 }
1142
1143 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1144 return ARCH_TIMER_VIRT_PPI;
1145
1146 if (IS_ENABLED(CONFIG_ARM64))
1147 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1148
1149 return ARCH_TIMER_PHYS_SECURE_PPI;
1150}
1151
1152static void __init arch_timer_populate_kvm_info(void)
1153{
1154 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1155 if (is_kernel_in_hyp_mode())
1156 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1157}
1158
1159static int __init arch_timer_of_init(struct device_node *np)
1160{
1161 int i, irq, ret;
1162 u32 rate;
1163 bool has_names;
1164
1165 if (arch_timer_evt) {
1166 pr_warn("multiple nodes in dt, skipping\n");
1167 return 0;
1168 }
1169
1170 has_names = of_property_present(np, "interrupt-names");
1171
1172 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
1173 if (has_names)
1174 irq = of_irq_get_byname(np, arch_timer_ppi_names[i]);
1175 else
1176 irq = of_irq_get(np, i);
1177 if (irq > 0)
1178 arch_timer_ppi[i] = irq;
1179 }
1180
1181 arch_timer_populate_kvm_info();
1182
1183 rate = arch_timer_get_cntfrq();
1184 arch_timer_of_configure_rate(rate, np);
1185
1186 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1187
1188 /* Check for globally applicable workarounds */
1189 arch_timer_check_ool_workaround(ate_match_dt, np);
1190
1191 /*
1192 * If we cannot rely on firmware initializing the timer registers then
1193 * we should use the physical timers instead.
1194 */
1195 if (IS_ENABLED(CONFIG_ARM) &&
1196 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1197 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1198 else
1199 arch_timer_uses_ppi = arch_timer_select_ppi();
1200
1201 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1202 pr_err("No interrupt available, giving up\n");
1203 return -EINVAL;
1204 }
1205
1206 /* On some systems, the counter stops ticking when in suspend. */
1207 arch_counter_suspend_stop = of_property_read_bool(np,
1208 "arm,no-tick-in-suspend");
1209
1210 ret = arch_timer_register();
1211 if (ret)
1212 return ret;
1213
1214 return arch_timer_common_init();
1215}
1216TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1217TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1218
1219#ifdef CONFIG_ACPI_GTDT
1220static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1221{
1222 int ret;
1223
1224 if (arch_timer_evt) {
1225 pr_warn("already initialized, skipping\n");
1226 return -EINVAL;
1227 }
1228
1229 ret = acpi_gtdt_init(table, NULL);
1230 if (ret)
1231 return ret;
1232
1233 /* The GTDT parser can't be bothered with the secure timer */
1234 for (int i = ARCH_TIMER_PHYS_NONSECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
1235 arch_timer_ppi[i] = acpi_gtdt_map_ppi(i);
1236
1237 arch_timer_populate_kvm_info();
1238
1239 /*
1240 * When probing via ACPI, we have no mechanism to override the sysreg
1241 * CNTFRQ value. This *must* be correct.
1242 */
1243 arch_timer_rate = arch_timer_get_cntfrq();
1244 ret = validate_timer_rate();
1245 if (ret) {
1246 pr_err(FW_BUG "frequency not available.\n");
1247 return ret;
1248 }
1249
1250 arch_timer_uses_ppi = arch_timer_select_ppi();
1251 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1252 pr_err("No interrupt available, giving up\n");
1253 return -EINVAL;
1254 }
1255
1256 /* Always-on capability */
1257 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1258
1259 /* Check for globally applicable workarounds */
1260 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1261
1262 ret = arch_timer_register();
1263 if (ret)
1264 return ret;
1265
1266 return arch_timer_common_init();
1267}
1268TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1269#endif
1270
1271int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
1272 enum clocksource_ids *cs_id)
1273{
1274 struct arm_smccc_res hvc_res;
1275 u32 ptp_counter;
1276 ktime_t ktime;
1277
1278 if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
1279 return -EOPNOTSUPP;
1280
1281 switch (arch_timer_uses_ppi) {
1282 case ARCH_TIMER_VIRT_PPI:
1283 case ARCH_TIMER_HYP_VIRT_PPI:
1284 ptp_counter = KVM_PTP_VIRT_COUNTER;
1285 break;
1286 default:
1287 ptp_counter = KVM_PTP_PHYS_COUNTER;
1288 }
1289
1290 arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
1291 ptp_counter, &hvc_res);
1292
1293 if ((int)(hvc_res.a0) < 0)
1294 return -EOPNOTSUPP;
1295
1296 ktime = (u64)hvc_res.a0 << 32 | hvc_res.a1;
1297 *ts = ktime_to_timespec64(ktime);
1298 if (cycle)
1299 *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
1300 if (cs_id)
1301 *cs_id = CSID_ARM_ARCH_COUNTER;
1302
1303 return 0;
1304}
1305EXPORT_SYMBOL_GPL(kvm_arch_ptp_get_crosststamp);