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258 lines · 6.7 KiB

1// SPDX-License-Identifier: GPL-2.0
2/*
3 * J-Core SoC PIT/clocksource driver
4 *
5 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
6 */
7
8#include <linux/kernel.h>
9#include <linux/slab.h>
10#include <linux/interrupt.h>
11#include <linux/clockchips.h>
12#include <linux/clocksource.h>
13#include <linux/sched_clock.h>
14#include <linux/cpu.h>
15#include <linux/cpuhotplug.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18
19#define PIT_IRQ_SHIFT 12
20#define PIT_PRIO_SHIFT 20
21#define PIT_ENABLE_SHIFT 26
22#define PIT_PRIO_MASK 0xf
23
24#define REG_PITEN 0x00
25#define REG_THROT 0x10
26#define REG_COUNT 0x14
27#define REG_BUSPD 0x18
28#define REG_SECHI 0x20
29#define REG_SECLO 0x24
30#define REG_NSEC 0x28
31
32struct jcore_pit {
33 struct clock_event_device ced;
34 void __iomem *base;
35 unsigned long periodic_delta;
36 u32 enable_val;
37};
38
39static void __iomem *jcore_pit_base;
40static struct jcore_pit __percpu *jcore_pit_percpu;
41
42static notrace u64 jcore_sched_clock_read(void)
43{
44 u32 seclo, nsec, seclo0;
45 __iomem void *base = jcore_pit_base;
46
47 seclo = readl(base + REG_SECLO);
48 do {
49 seclo0 = seclo;
50 nsec = readl(base + REG_NSEC);
51 seclo = readl(base + REG_SECLO);
52 } while (seclo0 != seclo);
53
54 return seclo * NSEC_PER_SEC + nsec;
55}
56
57static u64 jcore_clocksource_read(struct clocksource *cs)
58{
59 return jcore_sched_clock_read();
60}
61
62static int jcore_pit_disable(struct jcore_pit *pit)
63{
64 writel(0, pit->base + REG_PITEN);
65 return 0;
66}
67
68static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
69{
70 jcore_pit_disable(pit);
71 writel(delta, pit->base + REG_THROT);
72 writel(pit->enable_val, pit->base + REG_PITEN);
73 return 0;
74}
75
76static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
77{
78 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
79
80 return jcore_pit_disable(pit);
81}
82
83static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
84{
85 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
86
87 return jcore_pit_disable(pit);
88}
89
90static int jcore_pit_set_state_periodic(struct clock_event_device *ced)
91{
92 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
93
94 return jcore_pit_set(pit->periodic_delta, pit);
95}
96
97static int jcore_pit_set_next_event(unsigned long delta,
98 struct clock_event_device *ced)
99{
100 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
101
102 return jcore_pit_set(delta, pit);
103}
104
105static int jcore_pit_local_init(unsigned cpu)
106{
107 struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
108 unsigned buspd, freq;
109
110 pr_info("Local J-Core PIT init on cpu %u\n", cpu);
111
112 buspd = readl(pit->base + REG_BUSPD);
113 freq = DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd);
114 pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);
115
116 clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);
117 enable_percpu_irq(pit->ced.irq, IRQ_TYPE_NONE);
118
119 return 0;
120}
121
122static int jcore_pit_local_teardown(unsigned cpu)
123{
124 struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
125
126 pr_info("Local J-Core PIT teardown on cpu %u\n", cpu);
127
128 disable_percpu_irq(pit->ced.irq);
129
130 return 0;
131}
132
133static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)
134{
135 struct jcore_pit *pit = dev_id;
136
137 if (clockevent_state_oneshot(&pit->ced))
138 jcore_pit_disable(pit);
139
140 pit->ced.event_handler(&pit->ced);
141
142 return IRQ_HANDLED;
143}
144
145static int __init jcore_pit_init(struct device_node *node)
146{
147 int err;
148 unsigned pit_irq, cpu;
149 unsigned long hwirq;
150 u32 irqprio, enable_val;
151
152 jcore_pit_base = of_iomap(node, 0);
153 if (!jcore_pit_base) {
154 pr_err("Error: Cannot map base address for J-Core PIT\n");
155 return -ENXIO;
156 }
157
158 pit_irq = irq_of_parse_and_map(node, 0);
159 if (!pit_irq) {
160 pr_err("Error: J-Core PIT has no IRQ\n");
161 return -ENXIO;
162 }
163
164 pr_info("Initializing J-Core PIT at %p IRQ %d\n",
165 jcore_pit_base, pit_irq);
166
167 err = clocksource_mmio_init(jcore_pit_base, "jcore_pit_cs",
168 NSEC_PER_SEC, 400, 32,
169 jcore_clocksource_read);
170 if (err) {
171 pr_err("Error registering clocksource device: %d\n", err);
172 return err;
173 }
174
175 sched_clock_register(jcore_sched_clock_read, 32, NSEC_PER_SEC);
176
177 jcore_pit_percpu = alloc_percpu(struct jcore_pit);
178 if (!jcore_pit_percpu) {
179 pr_err("Failed to allocate memory for clock event device\n");
180 return -ENOMEM;
181 }
182
183 irq_set_percpu_devid(pit_irq);
184 err = request_percpu_irq(pit_irq, jcore_timer_interrupt,
185 "jcore_pit", jcore_pit_percpu);
186 if (err) {
187 pr_err("pit irq request failed: %d\n", err);
188 free_percpu(jcore_pit_percpu);
189 return err;
190 }
191
192 /*
193 * The J-Core PIT is not hard-wired to a particular IRQ, but
194 * integrated with the interrupt controller such that the IRQ it
195 * generates is programmable, as follows:
196 *
197 * The bit layout of the PIT enable register is:
198 *
199 * .....e..ppppiiiiiiii............
200 *
201 * where the .'s indicate unrelated/unused bits, e is enable,
202 * p is priority, and i is hard irq number.
203 *
204 * For the PIT included in AIC1 (obsolete but still in use),
205 * any hard irq (trap number) can be programmed via the 8
206 * iiiiiiii bits, and a priority (0-15) is programmable
207 * separately in the pppp bits.
208 *
209 * For the PIT included in AIC2 (current), the programming
210 * interface is equivalent modulo interrupt mapping. This is
211 * why a different compatible tag was not used. However only
212 * traps 64-127 (the ones actually intended to be used for
213 * interrupts, rather than syscalls/exceptions/etc.) can be
214 * programmed (the high 2 bits of i are ignored) and the
215 * priority pppp is <<2'd and or'd onto the irq number. This
216 * choice seems to have been made on the hardware engineering
217 * side under an assumption that preserving old AIC1 priority
218 * mappings was important. Future models will likely ignore
219 * the pppp field.
220 */
221 hwirq = irq_get_irq_data(pit_irq)->hwirq;
222 irqprio = (hwirq >> 2) & PIT_PRIO_MASK;
223 enable_val = (1U << PIT_ENABLE_SHIFT)
224 | (hwirq << PIT_IRQ_SHIFT)
225 | (irqprio << PIT_PRIO_SHIFT);
226
227 for_each_present_cpu(cpu) {
228 struct jcore_pit *pit = per_cpu_ptr(jcore_pit_percpu, cpu);
229
230 pit->base = of_iomap(node, cpu);
231 if (!pit->base) {
232 pr_err("Unable to map PIT for cpu %u\n", cpu);
233 continue;
234 }
235
236 pit->ced.name = "jcore_pit";
237 pit->ced.features = CLOCK_EVT_FEAT_PERIODIC
238 | CLOCK_EVT_FEAT_ONESHOT
239 | CLOCK_EVT_FEAT_PERCPU;
240 pit->ced.cpumask = cpumask_of(cpu);
241 pit->ced.rating = 400;
242 pit->ced.irq = pit_irq;
243 pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;
244 pit->ced.set_state_periodic = jcore_pit_set_state_periodic;
245 pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;
246 pit->ced.set_next_event = jcore_pit_set_next_event;
247
248 pit->enable_val = enable_val;
249 }
250
251 cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,
252 "clockevents/jcore:starting",
253 jcore_pit_local_init, jcore_pit_local_teardown);
254
255 return 0;
256}
257
258TIMER_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);