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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * (C) 2004-2006 Sebastian Witt <[email protected]>
4 *
5 * Based upon reverse engineered information
6 *
7 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
8 */
9
10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/cpufreq.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19
20#define NFORCE2_XTAL 25
21#define NFORCE2_BOOTFSB 0x48
22#define NFORCE2_PLLENABLE 0xa8
23#define NFORCE2_PLLREG 0xa4
24#define NFORCE2_PLLADR 0xa0
25#define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
26
27#define NFORCE2_MIN_FSB 50
28#define NFORCE2_SAFE_DISTANCE 50
29
30/* Delay in ms between FSB changes */
31/* #define NFORCE2_DELAY 10 */
32
33/*
34 * nforce2_chipset:
35 * FSB is changed using the chipset
36 */
37static struct pci_dev *nforce2_dev;
38
39/* fid:
40 * multiplier * 10
41 */
42static int fid;
43
44/* min_fsb, max_fsb:
45 * minimum and maximum FSB (= FSB at boot time)
46 */
47static int min_fsb;
48static int max_fsb;
49
50MODULE_AUTHOR("Sebastian Witt <[email protected]>");
51MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
52MODULE_LICENSE("GPL");
53
54module_param(fid, int, 0444);
55module_param(min_fsb, int, 0444);
56
57MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
58MODULE_PARM_DESC(min_fsb,
59 "Minimum FSB to use, if not defined: current FSB - 50");
60
61/**
62 * nforce2_calc_fsb - calculate FSB
63 * @pll: PLL value
64 *
65 * Calculates FSB from PLL value
66 */
67static int nforce2_calc_fsb(int pll)
68{
69 unsigned char mul, div;
70
71 mul = (pll >> 8) & 0xff;
72 div = pll & 0xff;
73
74 if (div > 0)
75 return NFORCE2_XTAL * mul / div;
76
77 return 0;
78}
79
80/**
81 * nforce2_calc_pll - calculate PLL value
82 * @fsb: FSB
83 *
84 * Calculate PLL value for given FSB
85 */
86static int nforce2_calc_pll(unsigned int fsb)
87{
88 unsigned char xmul, xdiv;
89 unsigned char mul = 0, div = 0;
90 int tried = 0;
91
92 /* Try to calculate multiplier and divider up to 4 times */
93 while (((mul == 0) || (div == 0)) && (tried <= 3)) {
94 for (xdiv = 2; xdiv <= 0x80; xdiv++)
95 for (xmul = 1; xmul <= 0xfe; xmul++)
96 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
97 fsb + tried) {
98 mul = xmul;
99 div = xdiv;
100 }
101 tried++;
102 }
103
104 if ((mul == 0) || (div == 0))
105 return -1;
106
107 return NFORCE2_PLL(mul, div);
108}
109
110/**
111 * nforce2_write_pll - write PLL value to chipset
112 * @pll: PLL value
113 *
114 * Writes new FSB PLL value to chipset
115 */
116static void nforce2_write_pll(int pll)
117{
118 int temp;
119
120 /* Set the pll addr. to 0x00 */
121 pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);
122
123 /* Now write the value in all 64 registers */
124 for (temp = 0; temp <= 0x3f; temp++)
125 pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
126}
127
128/**
129 * nforce2_fsb_read - Read FSB
130 *
131 * Read FSB from chipset
132 * If bootfsb != 0, return FSB at boot-time
133 */
134static unsigned int nforce2_fsb_read(int bootfsb)
135{
136 struct pci_dev *nforce2_sub5;
137 u32 fsb, temp = 0;
138
139 /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
140 nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
141 PCI_ANY_ID, PCI_ANY_ID, NULL);
142 if (!nforce2_sub5)
143 return 0;
144
145 pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
146 fsb /= 1000000;
147
148 pci_dev_put(nforce2_sub5);
149
150 /* Check if PLL register is already set */
151 pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
152
153 if (bootfsb || !temp)
154 return fsb;
155
156 /* Use PLL register FSB value */
157 pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
158 fsb = nforce2_calc_fsb(temp);
159
160 return fsb;
161}
162
163/**
164 * nforce2_set_fsb - set new FSB
165 * @fsb: New FSB
166 *
167 * Sets new FSB
168 */
169static int nforce2_set_fsb(unsigned int fsb)
170{
171 u32 temp = 0;
172 unsigned int tfsb;
173 int diff;
174 int pll = 0;
175
176 if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
177 pr_err("FSB %d is out of range!\n", fsb);
178 return -EINVAL;
179 }
180
181 tfsb = nforce2_fsb_read(0);
182 if (!tfsb) {
183 pr_err("Error while reading the FSB\n");
184 return -EINVAL;
185 }
186
187 /* First write? Then set actual value */
188 pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
189 if (!temp) {
190 pll = nforce2_calc_pll(tfsb);
191
192 if (pll < 0)
193 return -EINVAL;
194
195 nforce2_write_pll(pll);
196 }
197
198 /* Enable write access */
199 temp = 0x01;
200 pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);
201
202 diff = tfsb - fsb;
203
204 if (!diff)
205 return 0;
206
207 while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
208 if (diff < 0)
209 tfsb++;
210 else
211 tfsb--;
212
213 /* Calculate the PLL reg. value */
214 pll = nforce2_calc_pll(tfsb);
215 if (pll == -1)
216 return -EINVAL;
217
218 nforce2_write_pll(pll);
219#ifdef NFORCE2_DELAY
220 mdelay(NFORCE2_DELAY);
221#endif
222 }
223
224 temp = 0x40;
225 pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);
226
227 return 0;
228}
229
230/**
231 * nforce2_get - get the CPU frequency
232 * @cpu: CPU number
233 *
234 * Returns the CPU frequency
235 */
236static unsigned int nforce2_get(unsigned int cpu)
237{
238 if (cpu)
239 return 0;
240 return nforce2_fsb_read(0) * fid * 100;
241}
242
243/**
244 * nforce2_target - set a new CPUFreq policy
245 * @policy: new policy
246 * @target_freq: the target frequency
247 * @relation: how that frequency relates to achieved frequency
248 * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
249 *
250 * Sets a new CPUFreq policy.
251 */
252static int nforce2_target(struct cpufreq_policy *policy,
253 unsigned int target_freq, unsigned int relation)
254{
255/* unsigned long flags; */
256 struct cpufreq_freqs freqs;
257 unsigned int target_fsb;
258
259 if ((target_freq > policy->max) || (target_freq < policy->min))
260 return -EINVAL;
261
262 target_fsb = target_freq / (fid * 100);
263
264 freqs.old = nforce2_get(policy->cpu);
265 freqs.new = target_fsb * fid * 100;
266
267 if (freqs.old == freqs.new)
268 return 0;
269
270 pr_debug("Old CPU frequency %d kHz, new %d kHz\n",
271 freqs.old, freqs.new);
272
273 cpufreq_freq_transition_begin(policy, &freqs);
274
275 /* Disable IRQs */
276 /* local_irq_save(flags); */
277
278 if (nforce2_set_fsb(target_fsb) < 0)
279 pr_err("Changing FSB to %d failed\n", target_fsb);
280 else
281 pr_debug("Changed FSB successfully to %d\n",
282 target_fsb);
283
284 /* Enable IRQs */
285 /* local_irq_restore(flags); */
286
287 cpufreq_freq_transition_end(policy, &freqs, 0);
288
289 return 0;
290}
291
292/**
293 * nforce2_verify - verifies a new CPUFreq policy
294 * @policy: new policy
295 */
296static int nforce2_verify(struct cpufreq_policy_data *policy)
297{
298 unsigned int fsb_pol_max;
299
300 fsb_pol_max = policy->max / (fid * 100);
301
302 if (policy->min < (fsb_pol_max * fid * 100))
303 policy->max = (fsb_pol_max + 1) * fid * 100;
304
305 cpufreq_verify_within_cpu_limits(policy);
306 return 0;
307}
308
309static int nforce2_cpu_init(struct cpufreq_policy *policy)
310{
311 unsigned int fsb;
312 unsigned int rfid;
313
314 /* capability check */
315 if (policy->cpu != 0)
316 return -ENODEV;
317
318 /* Get current FSB */
319 fsb = nforce2_fsb_read(0);
320
321 if (!fsb)
322 return -EIO;
323
324 /* FIX: Get FID from CPU */
325 if (!fid) {
326 if (!cpu_khz) {
327 pr_warn("cpu_khz not set, can't calculate multiplier!\n");
328 return -ENODEV;
329 }
330
331 fid = cpu_khz / (fsb * 100);
332 rfid = fid % 5;
333
334 if (rfid) {
335 if (rfid > 2)
336 fid += 5 - rfid;
337 else
338 fid -= rfid;
339 }
340 }
341
342 pr_info("FSB currently at %i MHz, FID %d.%d\n",
343 fsb, fid / 10, fid % 10);
344
345 /* Set maximum FSB to FSB at boot time */
346 max_fsb = nforce2_fsb_read(1);
347
348 if (!max_fsb)
349 return -EIO;
350
351 if (!min_fsb)
352 min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
353
354 if (min_fsb < NFORCE2_MIN_FSB)
355 min_fsb = NFORCE2_MIN_FSB;
356
357 /* cpuinfo and default policy values */
358 policy->cpuinfo.min_freq = min_fsb * fid * 100;
359 policy->cpuinfo.max_freq = max_fsb * fid * 100;
360
361 return 0;
362}
363
364static struct cpufreq_driver nforce2_driver = {
365 .name = "nforce2",
366 .flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
367 .verify = nforce2_verify,
368 .target = nforce2_target,
369 .get = nforce2_get,
370 .init = nforce2_cpu_init,
371};
372
373#ifdef MODULE
374static const struct pci_device_id nforce2_ids[] = {
375 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 },
376 {}
377};
378MODULE_DEVICE_TABLE(pci, nforce2_ids);
379#endif
380
381/**
382 * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
383 *
384 * Detects nForce2 A2 and C1 stepping
385 *
386 */
387static int nforce2_detect_chipset(void)
388{
389 nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
390 PCI_DEVICE_ID_NVIDIA_NFORCE2,
391 PCI_ANY_ID, PCI_ANY_ID, NULL);
392
393 if (nforce2_dev == NULL)
394 return -ENODEV;
395
396 pr_info("Detected nForce2 chipset revision %X\n",
397 nforce2_dev->revision);
398 pr_info("FSB changing is maybe unstable and can lead to crashes and data loss\n");
399
400 return 0;
401}
402
403/**
404 * nforce2_init - initializes the nForce2 CPUFreq driver
405 *
406 * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
407 * devices, -EINVAL on problems during initialization, and zero on
408 * success.
409 */
410static int __init nforce2_init(void)
411{
412 /* TODO: do we need to detect the processor? */
413
414 /* detect chipset */
415 if (nforce2_detect_chipset()) {
416 pr_info("No nForce2 chipset\n");
417 return -ENODEV;
418 }
419
420 return cpufreq_register_driver(&nforce2_driver);
421}
422
423/**
424 * nforce2_exit - unregisters cpufreq module
425 *
426 * Unregisters nForce2 FSB change support.
427 */
428static void __exit nforce2_exit(void)
429{
430 cpufreq_unregister_driver(&nforce2_driver);
431 pci_dev_put(nforce2_dev);
432}
433
434module_init(nforce2_init);
435module_exit(nforce2_exit);